Digital frequency detector
AssigneeE. F. Johnson Company
InventorMervin L. Grindahl
Life of this patent
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Abstract
A frequency detector completely implemented with digital logic circuitry is disclosed. The frequency detector hereof employs a unique phase locked loop digitally implemented with asynchronous ripple counters, and a digitally implemented amplitude comparator and signal integrator. The detector is especially adapted for implementation in CMOS hardware, or similar hardware having low current drain characteristics. The selectivity of the detector can be set to a narrow bandwidth for excellent noise discrimination characteristics.
Claims37
A digital phase locked loop for receiving an input pulse train having an input frequency and for generating an output pulse train having a frequency and duty cycle which approach predetermined values relative to the input pulse train when the input frequency is within a predetermined frequency lock range comprising:
- clock means for generating a clock pulse train having a constant frequency;
- feedback means operably coupled to the clock means for generating a feedback pulse train having a frequency within the predetermined frequency lock range, the predetermined frequency lock range having a lower limit equal to a first fraction of the clock frequency and an upper limit equal to a second fraction of the clock frequency:
- comparison means operably coupled to the feedback means for receiving the input pulse train and comparing the input pulse train and the feedback pulse train and generating the output pulse train, the output pulse train having a duty cycle corresponding to the coincidence between the input pulse train and the feedback pulse train;
- and
- pulse inserter means operably coupled to the feedback means and the clock means and the comparison means for generating a modified clock pulse train in response to the duty cycle of the output pulse train, whereby the modified clock pulse train is received by the feedback means and the frequency of the feedback pulse train is continuously modified to approach the input frequency when the input frequency is within the predetermined frequency lock range.
A digital phase locked loop, comprising:
- input means for receiving an input signal pulse train;
- clock means for generating a master clock pulse train having a master clock pulse train frequency;
- pulse inserter means operably coupled to the clock means for selectively inserting additional pulses into the master clock pulse train to generate a modified clock pulse train having a modified clock pulse train frequency;
- feedback means operably coupled to the pulse inserter means for generating a feedback signal pulse train responsive to the modified clock pulse train frequency;
- and
- comparator means operably coupled to the input means and the feedback means for providing a pulse inserter actuating signal in response to the comparative values of the input signal pulse train and the feedback signal pulse train, whereby the pulse inserter is selectively actuated by the pulse inserter actuating signal to insert pulses into the master clock pulse train in response to the comparative values of the input signal and the feedback signal, and the feedback signal is thereby continuously modified to approach a predetermined value relative to the input signal.
A digital phase locked loop, comprising:
- input means for receiving an input signal pulse train;
- clock means for generating a master clock pulse train having a master clock pulse train frequency;
- frequency altering means operably coupled to the clock means for selectively modifying the master clock pulse train, thereby generating a modified clock pulse train having a modified clock pulse train frequency;
- feedback means operably coupled to the frequency altering means for generating a feedback signal pulse train correlating to the modified clock pulse train frequency;
- and
- comparator means operably coupled to the input means and the feedback means for providing a frequency altering means actuating signal in response to the comparative values of the input signal pulse train and the feedback signal pulse train, whereby the frequency altering means are selectively actuated by the actuating signal to alter the master clock pulse train in response to the comparative values of the input signal and the feedback signal, and the feedback signal is thereby continuously modified to approach a predetermined value relative to the input signal.
A method of implementing a digital phase locked loop having a specified frequency lock range comprising:
- generating a master clock signal having a constant clock frequency;
- generating a feedback pulse train having a frequency within the specified frequency lock range;
- receiving an input pulse train;
- comparing the input pulse train and the feedback pulse train and generating a pulse inserter signal in response to the comparative values of the input pulse train and the feedback pulse train;
- modifying the feedback pulse train by inserting or not inserting additional pulses into the feedback pulse train in response to the pulse inserter signal, so that the feedback pulse train approaches a predetermined value relative to the input pulse train.
A digital frequency detector for receiving an input pulse train having an input frequency and generating an output signal if the input frequency is within a predetermined frequency lock range for a predefined portion of a preselected time period comprising:
- clock means for generating a clock pulse train having a constant frequency;
- a digital phase locked loop operably connected to the clock means for receiving the input pulse train and generating an output pulse train having a frequency and duty cycle which approach predetermined values relative to the input pulse train when the input frequency is within the predetermined frequency lock range;
- integrator means operably connected to the digital phase locked loop and the clock means for determining an amount of time during the preselected time period that the input frequency is within the predetermined frequency lock range;
- and
- comparator means operably connected to the integrator means for generating an output signal when the amount of time determined by the integrator means exceeds the predefined portion.
A method for detecting whether the frequency of an input pulse train is within a specified frequency range for a specified time period, comprising:
- generating a master clock signal having a constant clock frequency;
- generating a feedback pulse train having a frequency within the specified frequency rang;
- generating an output pulse train by comparing the input pulse train with the feedback pulse train;
- modifying the feedback pulse train when the input pulse train and the feedback pulse train do not coincide;
- comparing the duty cycle of the output pulse train to an established threshold value greater than fifty percent;
- and
- generating an output signal when the duty cycle of the output pulse train exceeds the threshold value for the specified time period.
Dependencies are inferred from the claim text.