Test enabling circuit for enabling overhead test circuitry in programmable devices

In a programmable memory device having a testing circuit, a test enabling circuit connected to said testing circuit, and an input means for receiving a test signal and a normal operational signal, said testing circuit and a normal operational circuit connected at a common node to said input means, wherein said improvement is said test enabling circuit which comprises:

• a first and second resistive means forming a voltage divider means between said input means and a voltage supply with a nodal point therebetween coupled to said testing circuit for providing a first signal at said nodal point in response to said operational signal without voltage division and a second signal at said nodal point in response to a single said test signal with voltage division, wherein said first resistive means is of a higher value than said second resistive means;
• and
• a clamping means to said nodal point for preventing said second signal from exceeding a specified potential.

In a programmable memory device having a test enabling circuit and a normal operational circuit sharing a common node, an input means for receiving a test signal and a normal operational signal, said normal operation circuit having an input protection circuit for protecting said operational circuit from electrostatic discharge (ESD), the improvement being said input protection circuit which comprises:

• a first diode means connected between a power supply and a nodal point for providing a sink for positive ESD;
• a second diode means connected between a ground potential and said nodal point for providing a sink for negative ESD;
• a third diode means having a reverse breakdown voltage equivalent to a magnitude of said test signal, said third diode means being connected between said nodal point and said second diode means for preventing current from flowing through said second diode means to said input means when said test signal is applied to said input means.