On-chip bias generator
AssigneeXerox Corporation
InventorHo-Dai Truong
Life of this patent
Estimating the term…
Abstract
An improved on-chip bias generator for producing a negative bias for the substrate of a VLSI FET chip for reducing the body effect and for increasing circuit speed. The improvement comprises active FETs to rectify a ring oscillator square wave output, thereby reducing the voltage losses in the rectifier and increasing the amount of voltage delivered to the substrate.
Claims4
An on-chip bias generator for providing a bias to the substrate of said chip of the type having oscillator means for producing a series of square waves, rectifying means for producing a negative bias voltage from said square waves, and a capacitor for coupling said square waves from said oscillator means to said rectifying means, an improved rectifying means comprising:
- a first FET for coupling the output side of said capacitor to said substrate,
- a second FET for coupling the output side of said capacitor to ground, and
- logic means responsive to the output of said oscillator means for allowing said first FET to conduct only when the square wave is at one level and for allowing said second FET to conduct only when the square wave is at the other level.
An on-chip bias generator for providing a bias to the substrate of said chip comprising:
- oscillator means for producing a series of square waves,
- a capacitor, one side connected to the output of said oscillator means,
- a first FET for coupling the other side of said capacitor to said substrate,
- a second FET for coupling the other side of said capacitor to ground, and
- logic means responsive to the output of said oscillator means for allowing said first FET to conduct only when the square wave is at one level and for allowing said second FET to conduct only when the square wave is at the other level.
Dependencies are inferred from the claim text.