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US 4,733,105 AGranted
CMOS output circuit
AssigneeOki Electric Industry Co., Ltd.
InventorsYasuhiro Shin, Kazuhiko Yamada
Life of this patent
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Abstract
A CMOS output circuit including CMOS inverters, is formed on a semiconductor substrate and N MOS switching transistors are provided. The output circuit is responsive to an external control signal for switching a plurality of reference voltages and delivering them as multiple-level drive signals. The CMOS output circuit furthermore includes PMOS switching circuits connected in parallel with each of a plurality of CMOS transfer gates, CMOS inverters, and N MOS switching transistors for preventing a latch-up phenomenon of the CMOS inverters from being produced. The PMOS switching circuits are on-off controlled by a control signal obtained by converting an amplitude level of an external control signal.
Claims9
A CMOS output circuit formed on a semiconductor substrate comprising:
- (a) a control signal level shifting circuit responsive to a plurality of external control signals for delivering a plurality of control signals respectively converted to different amplitude levels;
- (b) a first switch means responsive to one of said control signals from said control signal level shifting circuit for selectively delivering a first reference voltage;
- (c) a second switch means responsive to one of said control signals from said control signal level shifting circuit for delivering a second reference voltage;
- (d) a third switch means responsive to one of said control signals from said control signal level shifting circuit for delivering a third reference voltage;
- (e) a fourth switch means responsive to one of said control signals from said control signal level shifting circuit for selectively delivering a fourth reference voltage;
- (f) a fifth switch means for selectively delivering one of said first, second, third, and fourth reference voltages to an output terminal based on one of said control signals from said control signal level shifting circuit;
- (g) a sixth switch means, connected in parallel with said first switch means, responsive to one of said external control signals for selectively delivering said first reference voltage;
- (h) a seventh switch means, connected in parallel with said second switch means, responsive to one of said external control signals for selectively delivering said second reference voltage;
- (i) an eighth switch means, connected in parallel with said third switch means, responsive to one of said external control signals for selectively delivering said third reference voltages;
- (j) a ninth switch means, connected in parallel to said fourth switch means, responsive to one of said external control signals for selectively delivering said fourth reference voltage;
- (k) a tenth switch means, connected between output nodes of said first and third switch means, and said output terminal, responsive to one of said external control signals for delivering said first or third reference voltage to said output terminal;
- and
- (l) an eleventh switch means, connected between outputs of said second and fourth switch means, and said output terminal, responsive to one of said external control signals for delivering said second or fourth reference voltage to said output terminal.
10 more elements
A CMOS output circuit formed on a semiconductor substrate comprising:
- (a) a multi-power source circuit for generating first, second, third, and fourth reference voltages;
- (b) a control signal level shifting circuit for converting a plurality of external control signals to control signals shifted to different amplitude levels;
- (c) complementary MOS switch means connected between first and second signal input nodes and on-off controlled by one of said control signals from said control signal level shifting circuit for selectively delivering a reference voltage at said first or second signal input node to a signal output terminal;
- (d) a first MOS switch means, connected between said first reference voltage and said first signal input node of said complementary switch means for selectively delivering said first reference voltage to said first signal node based on one of said control signals from said control signal level shifting circuit;
- (e) a second MOS switch means, connected between said second reference voltage and said first signal input node of said complementary MOS switch for selectively delivering said second reference voltage to said first signal node based on one of said control signals from said control signal level shifting circuit;
- (f) a third MOS switch means connected between said third reference voltage and said second signal node of said complementary MOS switch means for selectively delivering said third reference voltage to said second signal node based on one of said control signals from said control signal level shifting circuit;
- (g) a fourth MOS switch means connected between said fourth reference voltage and said second signal node of said complementary MOS switch means for selectively delivering said fourth reference voltage to said second node based on one of said control signals from said control signal level shifting circuit;
- (h) a fifth MOS switch means connected between said first reference voltage and said first signal input node for selectively delivering said first reference voltage to said first node based on one of said external control signals;
- (i) a sixth MOS switch means connected between said third reference voltage and said second signal input node for selectively delivering said third reference voltage to said second node based on one of said external control signals;
- (j) a seventh MOS switch means connected between said first signal input node and said signal output terminal for selectively delivering a reference voltage at said first signal input node to said output terminal based on one of said external control signals;
- (k) an eighth MOS switch means connected between said second signal input node and said signal output terminal for selectively delivering a reference voltage at said second signal input node to said output terminal based on one of said external control signals;
- and
- (l) a ninth MOS switch means connected between said fourth reference voltage and said second signal input node for selectively delivering said fourth reference voltage to said second signal input node based on one of said external control signal.
10 more elements
Dependencies are inferred from the claim text.