Method of making complementary field effect transistors
AssigneeFujitsu Limited
InventorTakashi Mimura
Life of this patent
Estimating the term…
Abstract
A semiconductor device, e.g., a complementary circuit comprising an n-channel transistor (Q.sub.n) utilizing a two-dimensional electron gas and a p-channel transistor (Q.sub.p) utilizing a two-dimensional hole gas, comprises: a semi-insulating GaAs substrate; a channel layer of an i-type GaAs having n.sup.+ -type source and drain regions and p.sup.+ -type source and drain regions; a buffer layer of an i-type AlGaAs preventing carriers from passing therethrough; first and second control layers of GaAs or AlGaAs having n-type or p-type conductivity, these layers being epitaxially formed in sequence on the substrate by an MBE method or an MOCVD method; and metal electrodes formed on the first and second control layers, n.sup.+ -type regions and p.sup.+ -type regions.
Claims7
A method of producing a semiconductor device comprising the steps of:
- epitaxially forming a channel layer of an undoped single crystalline semiconductor on a semi-insulating single crystalline substrate;
- epitaxially forming a buffer layer of an undoped single crystalline semiconductor on said channel layer;
- epitaxially and selectively forming a first control layer of a doped single crystalline semiconductor on said buffer layer;
- epitaxially and selectively forming a second control layer of a doped single crystalline semiconductor on said buffer layer;
- forming a first control electrode and a second control electrode on said first control layer and said second control layer and said second control layer, respectively;
- forming a pair of impurity regions of a first conductivity type in said channel layer;
- forming a pair of impurity regions of a second conductivity type, opposite said first conductivity type, in said channel layer;
- and
- forming electrodes on said impurity regions, respectively.
Dependencies are inferred from the claim text.