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US 4,731,843 AGranted
Method and device of increasing the execution speed of cipher feedback mode of the DES by an arbitrary multiplier
AssigneeParadyne Corporation
InventorKurt E. Holmquist
Life of this patent
Estimating the term…
Abstract
In an encryption system comprising DES in a cipher feedback mode of k bits, a plain text bit stream is fed into n individual DES encryptors. The DES encryptor operates in parallel from a common input register containing cipher text bit streams so that the overall throughput of the system is increased approximately by a factor of n. If k=1 then the system is self-synchronizing.
Claims4
A data encryption system for encrypting a stream of data bits, comprising:
- a serial in, parallel out register for receiving a stream of plaintext bits;
- a plurality of exclusive-or gates connected in parallel to outputs of said serial in, parallel out register and not in series with each other;
- a cipher text register connected to parallel outputs of said exclusive-or gates and having an output which can be transmitted to a decryptor;
- an input register connected to an output of said cipher text register and functioning to receive in series and store encrypted data blocks, each encrypted data block containing k bits;
- a plurality of encryptor circuits connected in parallel to outputs of said input register and having parallel outputs to said exclusive-or gates and functioning to substantially simultaneously process and then output in parallel selected bits from said encrypted data blocks to said plurality of exclusive-or gates.
2 more elements
A method of encrypting a stream of nk data bits comprising the steps of:
- feeding the data bits serially into a serial in parallel out plain text register of nk bits;
- combining bits from each k-bit segment from said plain text register with bits from a plurality of encryptor circuits in a plurality of exclusive-or gates connected in parallel between said plain text register and said encryptor circuits and not in series with each other to generate cipher bit blocks;
- sending said cipher bit blocks in parallel from said exclusive-or gates to a cipher text register;
- outputting said cipher bit blocks from said cipher text register to a decryptor and to an input register;
- storing encrypted data blocks in said input register, each encrypted data block containing k bits;
- outputting said encrypted data blocks in parallel to a plurality of encryptor circuits;
- substantially simultaneously processing said encrypted data blocks in said encryptor circuits;
- and
- outputting bits from said processed encrypted data blocks in parallel to said plurality of exclusive-or gates.
6 more elements
Dependencies are inferred from the claim text.