Circuit for implementing a low accumulated disparity code in high data rate digital transmission, and a coding method using such a circuit

A circuit for implementing a low accumulated disparity code for high data rate digital transmission of information grouped in the form of x-digit binary words, with an n-th word having a sum Sn equal to one half of the difference between the number of 1-bits and the number of 0-bits in said word, said circuit comprising:

• a calculating circuit for calculating said sum Sn for a sequence of values of n;
• a calculating unit for calculating the accumulated disparity for said sequence of values of n:
• ##EQU5## a comparator circuit for comparing the signs of .SIGMA..sub.n-1 and Sn;
• and
• an encoding circuit for encoding the n-th word;
• the overall coding circuit including the improvement whereby said unit for calculating the accumulated disparity comprises a first unit for calculating the sum .SIGMA..sub.n =.SIGMA..sub.n-1 +Sn and a second calculating unit for calculating the difference .SIGMA.'.sub.n =.SIGMA..sub.n-1 -Sn disposed in parallel, with the sign comparator circuit having an output which is directly connected to a reset to zero input for the first calculating unit, to a control input of the encoding circuit, and to one of the inputs to said encoding circuit to form an (x+1)-th output bit from said encoding circuit, and indirectly via an inverter to a reset to zero input for the second calculating unit.