On-chip test circuitry for an ECL PROM
AssigneeMotorola, Inc.
InventorRajnish Maini
Life of this patent
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Abstract
An improved programmable read only memory having a plurality of input pins and a plurality of memory elements is provided for testing the functionality and performance of the device without programming the memory. One of a combination of input signals applied to the input pins selects one of the memory elements for providing an output representative of the state of the memory element. A test circuit is coupled between the input pins and both the memory elements and a plurality of test memory elements for deselecting the memory elements and selecting the test memory elements.
Claims29
A memory circuit comprising:
- a first plurality of input pins including a first and a second input pin;
- a second plurality of input pins including a third and a fourth input pin;
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory elements, wherein each of said memory elements are uniquely coupled between one of said plurality of word lines and one of said plurality of bit lines;
- at least one test word line;
- at least one test bit line;
- a first plurality of test memory elements arranged in one or more rows, wherein each of said first plurality of test memory elements are uniquely coupled between one of said test word lines and one of either said bit lines or said test bit lines;
- a second plurality of test memory elements arranged in one or more columns, wherein each of said second plurality of test memory elements are uniquely coupled between one of said test bit lines and one of either said word lines or said test word lines;
- first means coupled to said plurality of word lines and said test word lines for selecting one of said word lines according to the digital states of a first plurality of input signals applied to said first plurality of input pins;
- second means coupled to said plurality of bit lines and said test bit lines for selecting one of said bit lines according to the digital states of a second plurality of input signals applied to said second plurality of input pins;
- third means coupled between said first plurality of input pins and said first means for selecting one of said word lines or said test word lines according to the digital states of the first plurality or input signals when an input signal applied to said first input pin exceeds a threshold voltage level;
- and
- fourth means coupled between said second plurality of input pins and said second means for selecting one of said bit lines or said test bit lines according to the digital states of the second plurality of input signals when an input signal applied to said second input pin exceeds a threshold voltage level.
An improved programmable read only memory having a plurality of memory elements arranged in a matrix of rows and columns, each of said memory elements in a row coupled to one of a plurality of word lines, each of said memory elements in a column coupled to one of a plurality of bit lines, a row decoder coupled to said plurality of word lines, a column decoder coupled to said plurality of bit lines, a first plurality of input pins, and a second plurality of input pins, said improvement comprising:
- a plurality of input buffers, each having a first input, a second input, a first output and a second output, said first input being coupled to one of said first or second plurality of input pins and said first and second outputs coupled to one of said row decoder or said column decoder, respectively wherein one of a combination of digital input signals applied to said first and second plurality of input pins selects one of said memory elements for providing an output representative of the state of said memory element;
- a plurality of test memory elements arranged in one or more rows and one or more columns of said matrix;
- and
- first means for selecting one of said plurality of test memory elements in response to a change in the voltage level of at least one of said digital input signals, said first means comprising:
- second means coupled between a first input pin of said first plurality of input pins and a second input of a first input buffer of said plurality of input buffers for altering an output signals of said first input buffer when an input signals applied to said first input pin exceeds a threshold voltage level;
- third means coupled between a second input pin of said first plurality of input pins and a second output of a second input buffer of said plurality of input buffers for alternating an output signal of said second input buffer when an input signal applied to said second input pin exceeds a threshold voltage level;
- fourth means coupled between a third input pin of said second plurality of inputs pins and a second input of a third input buffer of said plurality of input buffers for altering an output signal of said third input buffer when an input signal applied to said third input pin exceeds a threshold voltage level;
- and
- fifth means coupled between a second input pin of said second plurality of input pins and a second output of a fourth input buffer of said plurality of input buffers for altering an output signal of said fourth input buffer when an input signal applied to said fourth input pin exceeds a threshold voltage level.
Dependencies are inferred from the claim text.