Integrated circuit with built-in indicator of internal repair
AssigneeNEC Corporation
InventorTakayuki Watanabe
Life of this patent
Estimating the term…
Abstract
A circuit for providing an identification signal indicative of whether or not an semiconductor device has a repaired or replaced portion therein. The circuit is enabled by a control signal which is used for controlling the semiconductor device and causes a change in power supply current flowing into the semiconductor device according to presence or absence of the repaired or replaced portion.
Claims12
A semiconductor device comprising a first voltage terminal receiving a first potential, a second voltage terminal receiving a second potential, a control terminal for receiving a control signal having first and second logic levels, a functional section coupled to said first voltage terminal, said second voltage terminal and said control terminal, said functional section being enabled when said control signal is at said first logic level, said functional section including at least one normal circuit, a redundant circuit having the same function as said normal circuit and a control circuit, said control circuit being coupled to said normal circuit and said redundant circuit, said control circuit being programmed such that said control circuit operatively enables a normal circuit which is good and enables said redundant circuit when at least one normal circuit is defective to utilize said redundant circuit in place of the defective normal circuit, said control circuit enabling the normal circuit and/or the redundant circuit when said control signal is at said first logic level, a first and a second switching means coupled in series between said first and second voltage terminals, said first switching means being made conductive in response to the first logic level of said control signal and made non-conductive in response to the second logic level of said control signal, said second switching means being made one of conductive or non-conductive when said redundant circuit is enabled in place of said normal circuit and made non-conductive or conductive, being opposite the state representing enabling of said redundant circuit, when said redundant circuit is not utilized, whereby it is detectable through a conductivity between said first and second voltage terminals whether said redundant circuit is utilized or not.
A semiconductor device comprising a plurality of groups of memory cells, a redundant group of memory cells, means for receiving address information, a control signal terminal receiving a control signal having a first and second logic level, a selection circuit coupled to said plurality of groups of memory cells and said redundant group of memory cells for selecting one group of memory cells in accordance with said address information when said control signal is at said first logic level, said selection circuit selecting said redundant group of memory cells when said address information designates such one of the groups of memory cells that includes at least one defective memory cell, a pair of power voltage terminals for receiving power voltages, a first field effect transistor having a source-drain path and a gate, a second field effect transistor having a source-drain path and a gate, first means for connecting the source-drain paths of said first and second field effect transistors in series between said pair of voltage terminals, second means coupled to the gate of said first field effect transistor for rendering said first field effect transistor conductive when said control signal is at said first logic level and non-conductive when said control signal is at said second logic level, and third means coupled to the gate of said second field effect transistor for rendering said second field effect transistor conductive when at least one defective memory cell is present in said plurality of groups of memory cells and non-conductive when said plurality of groups of memory cells are all good, whereby a current flows between said pair of power voltage terminals via said first and second field effect transistors when at least one defective memory cells is present in said plurality of groups of memory cells.
A semiconductor device comprising plural groups of memory cells, a redundant group of memory cells, means for receiving address information, a control signal terminal receiving a control signal having first and second logic level, a selection circuit coupled to said plural groups of memory cells and said redundant group of memory cells for selecting one group of memory cells in accordance with said address information when said control signal is at said first logic level, said selection circuit selecting said redundant group of memory cells when said address information designates such one group of memory cells that includes at least one defective memory cells, a pair of power voltage terminals for receiving power voltages, a first field effect transistor having a source-drain path and a gate, a second field effect transistor having a source-drain and a gate, first means for connecting the source-drain paths of said first and second field effect transistors in series between said pair of voltage terminals, second means coupled to the gate of said first field effect transistor for rendering said first field effect transistor conductive when said control signal is at said first logic level and non-conductive when said control signal is at said second logic level, and third means coupled to the gate of said second field effect transistor for rendering said second field effect transistor conductive only when said selection circuit selects said redundant group of memory cells, whereby a current flows between said pair of power voltage terminals via said first and second field effect transistors when a memory cell or cells of said redundant group of memory cells are selected.
Dependencies are inferred from the claim text.