Memory timing and control apparatus

A memory option board for expanding an initial memory capacity of a main memory unit having a plurality of storage locations defining said initial memory capacity, said storage locations being addressable by the same plurality of address signals, said unit being included as part of a basic logic board into which said option board plugs, said option board including:

• a memory section having from one up to a predetermined number of rows of memory chips, said rows of chips providing a plurality of storage locations corresponding to a predetermined amount of expanded memory, and each of said memory chips of each of said rows including a row address strobe input terminal;
• and,
• a control section including:
• an addressable programmable memory having a plurality of locations, said locations including information coded for specifying said amount of expanded memory included on said option board, said programmable memory having a plurality of input terminals connected to receive a portion of said same plurality of address signals used for accessing storage locations within said main memory and said memory section during each memory cycle, an enabling input terminal connected to receive a timing signal from said logic board and a plurality of output terminals, each output terminal being connected to said row address strobe input terminal of each of said chips of a predetermined one of said predetermined number of rows and said programmable memory in response to each portion of said plurality of address signals and said timing signal received from said logic board generating an output signal at a selected one of said output terminals for an interval defined by the duration of said timing signal, the state of said output signal defining when access to storage locations within said row of memory chips specified by said portion is permitted.

A method of constructing a memory option board which expands the initial memory capacity of a primary system which is addressable by n number of address signals by a number of different increments of memory, said method comprising the steps of:

• (a) constructing said memory option board to include a memory section and a control section;
• (b) mounting in said memory section, m rows of addressable memory chips for expanding said inital memory capacity by said different increments of memory, each chip having a row address strobe (RAS) input terminal;
• (c) mounting in said control section, a programmable read only memory (PROM) having an enabling input terminal, n number of input terminals, 2.sup.n number of storage locations, each containing at least n number of bit locations, and m number of output terminals connected to said RAS terminals of a corresponding one of said m rows;
• (d) coding said 2.sup.n storage locations of said PROM, for providing output signals for enabling said m rows of memory chips for access as a function of a preselected increment of expanded memory being provided by said board memory section;
• and,
• (e) connecting said enabling input terminal and said n number of input terminals to receive a timing signal and said n number of address signals from said primary system for conditioning said PROM to generate output signals on different ones of said m number of output terminals, each of said output signals having a duration established by said timing signal and the stages of said output signals enabling access to memory locations in said rows specified by the coding of said address signals only for said preselected increment of expanded memory being provided thereby maintaining system integrity.