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AssigneeMotorola, Inc.
InventorsDavid Mothersole, Douglas B. MacGregor, John Zolnowsky
Estimating the term…
A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
A first data processor adapted for coordinating the execution of an instruction received for execution by said first processor with a second data processor responsive to a unique address comprised of a general address portion and a value unique to the second data processor contained in an address field of said instruction, the first data processor comprising:
Dependencies are inferred from the claim text.