System for simultaneous transmission of data blocks or vectors between a memory and one or a number of data-processing units

A system for simultaneous transmission of vectors of data blocks between plural memory cells and a plurality of data-processing units designed for asychronous operation with respect to each other, said system comprising:

• a group of memory cells composed of a whole number N of storage logic arrays each comprising any whole number n of physical arrays each having q storage locations;
• an interconnection network interposed between the group of memory cells and the data-processing units for simultaneously establishing connections between the memory arrays and said processing units;
• a control device coupled to said interconnection network for controlling the connection paths within the interconnection network;
• a plurality of addressing logic devices each controlled respectively by one of the plurality data-processing unit for addressing the locations of the memory to which each unit requests access and performing transfer of the vectors or data blocks contained in the corresponding locations;
• wherein the N.n physical arrays of the memory being juxtaposed and numbered in order of natural integers 0, . . . so as to form an ordered matrix base of storage locations, each storage location in a physical array being located at the point of intersection of a line and a column of the matrix base and being also numbered on each line in the order of increasing magnitude of the matural integers from the start-of-line location contained in the first physical array denominated as the 0 array of the momory to the end-of-line location contained in the last physical array of the memory, all of the start-of-line locations of the memory being located within a first physical array;
• wherein each of said addressing logic device comprises:
• means for determining the address of sach location in the physical array by computing the modulo address (N.n) of each location in the physical array from its sequence number in the memory to allow for the multiple data-processing units to access the same storage array on a simultaneous basis;
• wherein said control logic device comprises means for establishing a connection between a requesting data-processing unit and the storage logic array containing the computed modulo address of the start of the vector or of the data block to be transferred and switching means in said control logic device for successively switching the requesting unit to the following storage logic arrays at the end of each data transfer between a logic array of the memory and the data-processing unit without interruption until the transfer of the last data item of the block or of the vector.