Semiconductor memory device with means to prevent word line breakage
AssigneesHitachi, Ltd., Hitachi Device Eng. Co., Ltd.
InventorsHisao Katto, June Sugiura, Nozomi Horino, Akira Endo, Yoshiharu Takeuchi, Yuji Arakawa
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Abstract
A semiconductor memory device having wiring formed next to word lines at the extreme ends of the memory cell arrays or next to word lines of the dummy cell arrays, in order to prevent such word lines from breaking or from becoming deformed. The wiring is irrelevant to the circuit operation, but is provided with a fixed potential, and is formed through the steps of forming the word lines. The wiring makes the processing conditions applied to the neighboring word lines the same as the processing conditions applied to other word lines.
Claims10
A semiconductor memory device comprising:
- at least one memory cell array including a plurality of memory cells that are formed in rows and in columns on a semiconductor substrate;
- a plurality of word lines formed in rows, said word lines being coupled to said memory cells that are arrayed in corresponding rows;
- a plurality of data lines formed in columns, said data lines being coupled to said memory cells that are arrayed in corresponding columns;
- contact holes formed by dry etching in an intermediate insulating film formed between said word lines and said data lines to couple said data lines and said memory cells together;
- and
- a film which is formed between said plurality of word lines formed in rows and a first peripheral edge of said memory cell array, said film being located on said semiconductor substrate at a location to prevent the thickness of a resist film for forming said contact holes from decreasing on the word lines which are located closest to said peripheral edge.
- wherein said data lines are comprised of aluminum, and wherein said word lines and said film are each comprised of a first layer of polycrystalline silicon and a second layer of silicide formed over said first layer.
Dependencies are inferred from the claim text.