Converter

#The present invention relates to an integral-type A/D or D/A converter.

#As an example of A/D converters, there has been known the integral-type A/D converter. In this integral-type A/D converter, an analog input signal is fed via a sampling switchelement to an integrator which consists of an operational amplifier and a capacitor. At the moment when the switch element is closed, the capacitor starts charging to the input voltage. The capacitor is connected with two constant current sources providing different supply currents through respective switches. At a time point when the sampling switch element is opened, the constant current sources have their switches closed, and the capacitor is discharged by the constant current sources. The two constant current sources provide currents I.sub.o and i.sub.o, which are set in magnitude to be, for example, I.sub.o :i.sub.o 2.sup.7 :1 or 128:1. Initially, the switch associated with the source of current I.sub.o is closed, causing the capacitor to start discharging, and the discharging time length until the capacitor voltage becomes the predetermined value is measured by an upper-bits counter. Subsequently, the switch associated with the source of current I.sub.o is opened and at the same time the switch associated with the source of current i.sub.o is closed, and the capacitor continues discharging until its voltage falls to zero volts, and the discharging time length is measured by a lower-bits counter. The count values left in the upper and lower bits counters in combination represent a 16-bit digital value as a result of A/D conversion for the input analog signal. The foregoing A/D converter is described in U.S. patent application Ser. No. 556,710 (filed on Nov. 25, 1983) by the applicant of the present invention, and a D/A converter using the same principle is described in U.S. Pat. No. 4,404,546 and U.S. patent application Ser. No. 432,845 (filed on Oct. 5, 1982).

#The foregoing conventional A/D converter operates at a conversion speed which is determined from the length of time after the upper 9-bit counter has started counting until the lower 7-bit counter ends the count operation. The upper 9-bit counter has a count capacity of 2.sup.9 (i.e., 512), while the lower 7-bit counter has a count capacity of 2.sup.7 (i.e., 128). Accordingly, the total count capacity of the upper 9-bit counter and lower 7-bit counter is 640. For a given sampling frequency of 48 kHz, for example, 640 counts must be completed in each sampling period. If it is intended to implement A/D conversion for two channels alternately on a time division basis, the clock generator needs to produce a master clock at a frequency: fm.sub.1 =2ch.times.48 kHz.times.640=61.44 MHz.

#FIG. 1 is a block diagram showing an embodiment of this invention;

#FIG. 2 is a waveform diagram used to explain the generation of a clock having a double frequency according to the embodiment;

#FIG. 3 is a waveform diagram used to explain the operation of the embodiment; and

#An embodiment of this invention will now be described with reference to the drawings.

#In FIG. 1, an operational amplifier 1 has an associated capacitor 2 connected between its inverting input terminal and output terminal, and an integrator is formed by these components. The output terminal of the operational amplifier 1 is connected through a resistor 4 to one end of a resistor 5, which has another end connected to the input terminal 6 of the converter. The resistors 4 and 5 have their common end connected via a switch circuit 3 to the inverting input terminal of the operational amplifier 1. The non-inverting input terminal of the operational amplifier 1 is grounded. The inverting input terminal of the operational amplifier 1 is connected to one terminal of a current source 9 providing a current value I.sub.o and another current source 10 providing a current value i.sub.o through switch circuits 7 and 8, respectively. Another terminal of each of the current sources 9 and 10 is grounded.

#The switch circuit 3 is controlled by sampling pulses Ps from a control circuit 14. When the switch circuit 3 is closed in response to a sampling pulse Ps, the input analog signal at the input terminal 6 is sampled and held in such a way that the capacitor 2 is charged to the input voltage Vin. When the switch circuit 3 is made open, the capacitor 2 is discharged by means of the current sources 9 and 10. The switch circuits 7 and 8 are controlled by a control circuit 14 so that the capacitor 2 is first discharged to a certain voltage level by the current source 9 of I.sub.o and then discharged successively by the current source 10 of i.sub.o. The current sources 9 and 10 have their current values I.sub.o and i.sub.o preset to have a relation I.sub.o /i.sub.o =128.