US 4,731,568 A · Error signal generator

Abstract

An error signal generator for generating a plurality of error signals for various control values, comprises a time controller for sequentially and periodically generating a plurality of status signals, the number of which corresponds to the number of the control values. A read-out signal generator receives reference signals and/or detection signals for generating a read-out signal in response to one of the reference signals selected by the associated status signal. There is provided a preset memory storing a plurality of preset digital values for the control values and responsive to the read-out signal so as to output to a bus the preset digital value designated by the associated status signal. A count memory responds to each status signal so as to read out the data to the bus from one of the memory areas designated by the associated status signal and then is rewritten with the data on the bus into the same memory area. An adder operates to periodically subtract a value of "1" from the data on the bus and to return the result of the subtraction to the bus. An error memory responds to each of the detection signals so as to write the data on the bus into one of the memory areas designated by the associated status signal. The respective memory areas provide the data stored therein as the error signals.

Claims4

Dependent claims

An error signal generator for generating a first error signal responsive to a first reference signal and a first detection signal and a second error signal responsive to a second reference signal and a second detection signal, comprising:

a time controller for periodically generating first and second status signals in response to a clock signal;
a preset memory storing first and second preset data and outputting to a bus line said first preset data when both of said first reference signal and said first status signal are present and said second preset data when both of said second reference signal and said second status signal are present;
a count memory having first and second memory areas and coupling to said bus line said first memory area in response to said first status signal and said second memory area in response to said second status signal;
means coupled to said bus line for subtracting a predetermined value from the data on said bus line and for returning the result of the subtraction to said bus line in response to each of said first and second status signals;
and
an error signal memory having third and fourth memory areas and storing at least one portion of the data on said bus line into said third memory area when both of said second detection signal and said second status signal are present, the data stored in said third and fourth memory areas being generated as said first and second error signals, respectively.

3 more elements

An error signal generator for generating first and second error signals in response to first and second detection signals, respectively, comprising:

a time controller for periodically generating first and second status signals in response to a clock signal;
means for generating a read-out signal when both of said first detection signal and said first status signal are present or when both of said second detection signal and said second status signal are present;
a preset memory for storing first and second preset data and for outputting to a bus line said first preset data in response to said read-out signal and said first status signal and said second preset data in response to said read-out signal and said second status signal;
a count memory having first and second memory areas and coupling to said bus line said first memory area in response to said first status signal and said second memory area in response to said second status signal;
means coupled to said bus line for subtracting a predetermined value from the data on said bus line and for returning the result of the subtraction to said bus line in response to each of said first and second status signals;
means responsive to said first and second detection signals and said first and second status signals for generating a write signal before the generation of said read-out signal;
and
an error signal memory having third and fourth memory areas and storing the data on said bus line into said third memory area in response to said write signal and said first status signal and into said fourth memory area in response to said write signal and said second status signal, the data stored in said third and fourth memory areas being generated as said first and second error signals, respectively.

5 more elements

Dependencies are inferred from the claim text.

Error signal generator

Life of this patent

Error signal generator

Life of this patent

Abstract

Claims4