US 4,731,553 AGranted

CMOS output buffer having improved noise characteristics

AssigneeTexas Instruments Incorporated

InventorsDavid A. Van Lehn, Edward H. Flaherty

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Abstract

A CMOS output buffer circuit which as improved noise characteristics is disclosed. The circuit has two stages, one having relatively fast response time for causing the output node to make a quick logic transition, and the other stage for providing steady-state drive of the output node. The transistors in the transition-driving stage are driven from power supply and reference supply nodes which are isolated from the power supply and reference supply nodes of the steady-state stage. For a low-to-high transition, the driving transistor in the steady-state stage, being p-channel, drives the output node to a full power supply level, which causes the driving transistor in the transition-driving stage to turn off, isolating the two power supply nodes of the two stages from one another. For a high-to-low transition, a feedback circuit serves to turn off the pull-down transistor of the transition-driving stage in order to isolate the two reference supply nodes of the two stages from one another. The steady-state stage is delayed, so that the noise from the initial transition does not appear at the power supply and reference supply nodes of the steady-state stage. The circuit also operates so that the output node can be put into a high-impedance state, allowing for common input/output utilization of the circuit.

Claims13

Dependent claims

An MOS logic circuit, having an input and having an output, and adapted for driving its output to a logic state responsive to the logic state received by its input, comprising:

a first MOS transistor, having its source-to-drain path connected between a first power supply node and the output node of the logic circuit, and having its gate coupled to the input of the logic circuit so that its source-to-drain path is conductive responsive to said input of said logic circuit being at a first logic state;
a second MOS transistor, having its source-to-drain path connected between the output node of the logic circuit and a first reference supply node, and having its gate coupled to the input of the logic circuit so that its source-to-drain path is conductive responsive to said input of said logic circuit being at a second logic state;
a third MOS transistor, having its source-to-drain path connected between the output node of the logic circuit and a second power supply node;
a fourth MOS transistor, having its source-to-drain path connected between the output node of the logic circuit and a second reference supply node;
a first delay means, connected between said input to said logic circuit and the gate of said third MOS transistor, for communicating the state of said input to said gate of said third MOS transistor so that the source-to-drain path of said third MOS transistor is conductive at a predetermined time after said input of said logic circuit is at said first logic state, said third MOS transistor charging said output of said circuit to a voltage which turns off said first MOS transistor;
a second delay means, connected between said input to said logic circuit and the gate of said fourth MOS transistor, for communicating the state of said input to said fourth MOS transistor so that the source-to-drain path of said fourth MOS transistor is conductive a predetermined time after the said input of said logic circuit is at said second logic state;
and
turn-off means, connected to the gate of said second MOS transistor, for turning off said second MOS transistor approximately as said source-to-drain path of said fourth MOS transistor becomes conductive responsive to said input of said logic circuit being at said second logic state;
wherein said first and second power supply nodes are at substantially the same voltage;
and wherein said first and second reference supply nodes are at substantially the same voltage, said voltage of said first and second reference supply nodes representative of a different logic state than that represented by the voltage of said first and second power supply nodes.

7 more elements

In an MOS output buffer circuit having an input node for receiving a logic signal having a first logic state and a second logic state, a first power supply node, a first reference supply node having a voltage representative of a different logic state from that represented by the voltage of said first power supply node, an output node, a first MOS transistor having its source-to-drain path connected between said first power supply node and said output node and having its gate coupled to said input node so that said first power supply node is connected to said output node responsive to said input node being at its first logic state, and a second MOS transistor having its source-to-drain path connected between said output node and said first reference supply node and having its gate coupled to said input node so that said first reference supply node is connected to said output node responsive to said input node being at its second logic state, said logic circuit thereby driving said output node to a voltage responsive to said logic state received by said input node, the improvement comprising:

a second power supply node being at substantially the same voltage as said first power supply node;
a second reference supply node being at substantially the same voltage as said first reference supply node;
an intermediate output node, coupled to said output node;
a third MOS transistor, having its source-to-drain path connected between said second power supply node and said intermediate output node, and having a gate;
a fourth MOS transistor, having its source-to-drain path connected between said second reference supply node and said intermediate output node, and having a gate;
a first coupling means for coupling said input node to said gate of said third MOS transistor in such a manner that said second power supply node is connected to said intermediate output node by said third MOS transistor at a predetermined delay time after said input node reaches its first logic state so that said output node is charged from said second power supply node to a voltage within a transistor threshold voltage of the voltage at the gate of said first MOS transistor;
a second coupling means for coupling said input node to said gate of said fourth MOS transistor in such a manner that said second reference supply node is connected to said intermediate output node by said fourth MOS transistor at a predetermined delay time after said input node reaches its second logic state;
and
means, connected to the gate of said second MOS transistor, for turning off said second MOS transistor responsive to the voltage of said output node approaching the voltage of said first reference supply node.

6 more elements

Dependencies are inferred from the claim text.