Loading patent…
AssigneeSociete pour l'Etude et la Fabrication des Circuits Integres Speciaux (EFCIS)
InventorsAlain Roche, Joseph Borel
Estimating the term…
A novel MOS transistor structure comprises electrodes of metallic silicide and especially tantalum silicide. In the case of the gate electrode, the silicide is directly in contact with an insulating thin-film layer. In the case of the drain and source electrodes, the silicide is directly in contact with the monocrystalline silicon. The method of fabrication is thus simplified while avoiding the use of polycrystalline silicon.
A method of fabrication of an integrated circuit, wherein said method comprises the following successive steps:
Dependencies are inferred from the claim text.
Drawings are temporarily unavailable. Open the PDF at USPTO
No related US applications are recorded in the indexed filing history.
Source or drain regions of field-effect devices: of igfets
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
Of FETs having insulated gates [IGFET]: having source and drain regions or source and drain extensions self-aligned to sides of the gate
Characterised by the materials: being Group IV materials, e.g. B-doped Si or undoped Ge
Term ended 24 Feb 2006 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention
The present invention relates to MOS integrated circuits having high integration density.
2. Description of the Prior Art
Other features of the invention will be more apparent upon consideration of the following description and accompanying drawings, wherein:
FIG. 1 illustrates the structure of an MOS transistor of a circuit fabricated by the method in accordance with the invention;
FIGS. 2 to 8 illustrate the successive fabrication steps required in order to obtain the final structure shown in FIG. 1.
FIG. 1 is a cross-section showing an MOS transistor formed in a monocrystalline silicon substrate 10. The transistor could also be formed in a case of opposite conductivity type with respect to the substrate (especially for integrated circuits which utilize the CMOS technology). The substrate in this instance is p-type, for example.
The transistor is formed in an active zone surrounded by a wall 12 of thick silicon oxide. In accordance with conventional practice, steps can be taken to ensure that the p-type substrate is more heavily doped beneath the thick oxide than in the active zone. By way of example, the oxide thickness is 5000 Angstroms.
A source region 14 heavily doped with an impurity of opposite conductivity type relative to the substrate and a drain region 16 doped in the same manner as the source region are formed on the surface of the substrate and are separated by a p-type channel region constituted by the substrate itself.