Semiconductor memory device

A semiconductor memory device comprising:

• a check bit memory cell array (32) for outputting write check bits for an on-chip error correcting function,
• said check bit memory cell array including an address signal line, a data input signal line and a data output signal line,
• switch means (10, 20, 30) for making said check bit memory cell array directly externally accessible,
• said switch means including means (10, 20, 30) operable for conveying an external address signal to said address signal line during a test mode, means for conveying external data to said data input signal line and means for conveying outputted data to said data output signal line,
• a write check bit generating circuit means (2) for generating write check bits on the basis of external data bits input thereto,
• said switch menas including a data input switching means (20) for effecting selective switching between said external data bits and the write check bits generated by said write check bit generating circuit means, thereby providing the selected bits to the data input signal line of said check bit memory cell array.

A semiconductor memory device with an on-chip error correcting function, comprising:

• write check bit generating means (2) for generating write check bits on the basis of inputted data bits,
• data input switching means (20) for effecting switching between said write check bits generated from said write check bit generating means and said inputted data bits to thereby output the selected bits,
• a data bit memory cell array (31) for storing said inputted data bits and outputting new data bits on the basis of the stored data bits,
• a check bit memory cell array (32) for generating new check bits on the basis of the write check bits generated from said write check bit generating means,
• address signal generating means (8) for generating address signals used to specify said data bit memory cell array (31) and said check bit memory cell array (32),
• address switching means (10) for effecting switching between the address signal from address siganl generating means and the address signal from the outside, thereby giving the selected address signal to said data bit memory cell array (31) and said check bit memory cell array (32),
• read check bit generating means (4) for generating read check bits on the basis of new data bits from said data bit memory cell array,
• syndrome generating circuit (5) for computing the exclusive-OR of the new write check bits from said check bit memory cell array and the check bits generated by said read check bit generating means,
• data correcting means (7) for correcting data stored in said data bit memory cell array on the basis of the syndrome generated from said syndrome generating means, and
• data output switching means (30) for effecting switching between check bits outputted from said check bit memory cell array and the output of said data correcting means (7).

A semiconductor memory device with an on-chip error correcting function comprising:

• write check bit generating means (2) for generating write check bits on the basis of inputted data bits,
• a data bit memory cell array (31) for storing said inputted data bits and outputting new data bits on the basis of the stored data bits, (continued)
• a check bit memory cell array (32) for generating new check bits on the basis of the write check bits generated from said write check bit generating means,
• read check bit generating means (4) for generating read check bits on the basis of new data bits from said data bit memory cell array,
• check bit switching means (90) for effecting selective switching between at least the write check bits generated from said write check bit generating means and the write check bits generated from said check bit memory cell array (32), and
• exclusive-OR operation means (5) for computing the exclusive-OR of the two classes of check bits outputted from said check bit switching means.