Digital integrated circuits
AssigneeInternational Computers Limited
InventorsPeter L. L. Desyllas, Finbar Naven
Life of this patent
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Abstract
A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.
Claims7
A digital integrated circuit comprising
- (a) at least one group of latches,
- (b) a serial input terminal and a serial output terminal connected to the latches,
- (c) means for producing a clock signal,
- (d) means for operating the group of latches in a user mode in which the group acts as at least one register with parallel inputs and outputs,
- (e) means for operating the group of latches in a hold mode in which the contents of all the latches in the group are preserved,
- (f) means for operating the groups of latches in a shift mode in which the latches are coupled together to form a serial shift path extending between the serial input terminal and the serial output terminal and data is stepped through this path by means of the clock signal,
- (g) a control input terminal for receiving a series of transfer pulses, and
- (h) a control circuit connected to the control input terminal and operable to put the group of latches into its hold mode and then, in response to each of the transfer pulses, to switch the group from the hold mode into the shift mode and then back into the hold mode.
Dependencies are inferred from the claim text.