Digital integrated circuits
AssigneeInternational Computers Limited
InventorsPeter L. L. Desyllas, Finbar Naven
Life of this patent
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Abstract
A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes: USER, HOLD, SHIFT and SELF-TEST modes. These modes are controlled by shifting a control function into a control shift register. When the shifting of the control shift register stops, a command is automatically loaded from the control shift register (or another source) into a command register, which controls the serial shift paths. The provision of a separate command register allows a new control function to be shifted into the control shift register while a preceding command is still active in the command register.
Claims9
A digital integrated circuit comprising:
- (a) a plurality of shift register latches connected together to form a plurality of serial shift paths in parallel between a serial data input terminal and a serial data output terminal, each path having a plurality of modes of operation,
- (b) a control shift register connected to the serial data input terminal to allow commands to be shifted serially into the control shift register,
- (c) a command register,
- (d) means for transferring a command in parallel from the control shift register into the command register, and
- (e) means for utilizing the contents of the command register to control the modes of operation of the shift paths.
A digital integrated circuit comprising:
- (a) plurality of shift register latches connected together to form a plurality of serial shift data paths in parallel between a serial data input terminal and a serial data output terminal, each path having a plurality of modes of operation,
- (a) a control shift register connected to the serial data input terminal to allow commands be shifted serially into the control shift register,
- (c) a command register,
- (d) transfer means for transferring a command in parallel from the control shift register into the command register,
- (e) means for utilising the contents of the command register to control the modes of operation of the shift paths,
- (f) means for receiving a series of transfer pulse signals and a control select signal,
- (g) means for enabling the control shift register for shifting upon occurrence of each said transfer pulse signal while said control select signal is present, and
- (h) means for detecting a first of said transfer pulse signals following removal of said control select signal to produce a transfer control signal which enables said transfer means to transfer a command into the command register.
A digital integrated circuit comprising:
- (a) a plurality of shift register latches connected together to form a plurality of serial shift data paths in parallel between a serial data input terminal and a serial data output terminal, each path having a plurality of modes of operation,
- (b) a control shift register connected to the serial data input terminal to allow commands to be shifted serially into the control shift register,
- (c) a command register,
- (d) transfer means for transferring a command in parallel from the control shift register into the command register,
- (e) means for utilising the contents of the command register to control the modes of operation of the shift paths,
- (f) a parity checking circuit for checking the contents of the control shift register to produce a parity fail signal if a parity error is detected,
- (g) means responsive to the parity fail signal for inhibiting transfer of a command from the control shift register into the command register,
- (h) means responsive to the parity fail signal for causing a hard-wired HOLD command to be loaded into the command register, and
- (i) means responsive to the hold command when in the command register for putting all the serial shift paths into a HOLD mode in which they are frozen in their existing states.
Dependencies are inferred from the claim text.