US 4,730,279 A · Static semiconductor memory device

Abstract

A memory cell array consists of a plurality of memory sections. A pair of bit lines are provided for each column, and word lines are provided each for each row in each memory section. One end of the current path of a first transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. One end of the current path of a second transistor is connected to the corresponding bit line. A predetermined voltage is applied to the other end of the current path of the first transistor. The current capacity of the first transistor is larger than that of the second transistor. After an address signal varies and a predetermined period elapses, the first transistor in the selected section turns on, the second transistor in the selected section turns off, the first transistor in the nonselected section turns off, and the second transistors in the nonselected section turns on. The bit lines in the selected section are charged for a predetermined period of time after the address signal changes, to pull up the voltages of the bit lines in the nonselected section to a power supply voltage. A row decoder renders the word line active in level after the first transistor connected to the bit lines of the selected section is turned off according to an address signal.

Claims11

Dependent claims

A semiconductor memory device comprising:

a memory cell array including memory cells arranged in a matrix of rows and columns, said array having a plurality of sections, each section including memory cells belonging to at least one column;
a plurality of bit lines for writing data to and reading data from said memory cells, a pair of said bit lines being provided for each column and connected to memory cells in the corresponding column;
word lines connected to corresponding memory cells to select memory cells in the row direction;
and
precharge means connected to said bit lines, for receiving and for detecting the contents of an address signal, said precharge means being responsive to said address signal to charge, during a predetermined period, said bit lines in at least one selected section which includes at least one memory cell designated by said address signal, and to charge said bit lines in at least one nonselected section.

2 more elements

A semiconductor memory device comprising:

a memory cell array including memory cells arrayed in a matrix, said array having a plurality of sections, each section including memory cells belonging to at least one column;
a pair of bit lines for writing and reading out data to and from said memory cells, each pair of said bit lines being provided for each column, said bit lines being connected to memory cells in the corresponding column;
word lines connected to corresponding memory cells to select memory cells in the row direction;
at least one first transistor and at least one second transistor connected to a corresponding at least one bit line and a terminal applied with a predetermined voltage;
precharge means, connected to said first second transistors, for receiving an address signal and for detecting the contents of said address signal and a change in the contents of said address signal, said precharge means turning on said first transistor connected to the bit line in a selected section which includes at least one memory cell designated by the address signal, during a predetermined period after a fixed period elapses from a change in the contents of the address signal, turning off said second transistor connected to the bit lines in said selected section, turning off said first transistor connected to the bit lines in at least one nonselected section, and turning on said second transistors connected to the bit lines in said nonselected section to charge the bit lines in said nonselected section;
and
a row decoder connected to said word lines, for receiving and for detecting the contents of said address signal and a change in the contents of said address signal, said row decoder activating, in response to said address signal, the voltage of the word line specified by the address signal, after the charge of the bit lines in said selected section by said precharge means is substantially completed, and said predetermined period of time elapses after the contents of the address signal change.

4 more elements

Dependencies are inferred from the claim text.

Static semiconductor memory device

Life of this patent

Static semiconductor memory device

Life of this patent

Abstract

Claims11