Circuit for biasing row of memory cells

A circuit for selecting a row of memory cells in an array of memory cells, said memory cells having a write mode for writing information into one of said selected memory cells, a low current mode for storing said information, and a read mode for reading said information in one of said selected memory cells, said array of memory cells including a first voltage terminal, a second voltage terminal, a plurality of word lines, a plurality of bit lines, wherein said memory cells are arranged in a matrix of rows and columns, each of said memory cells in a row coupled between said first voltage terminal and one of said word lines, each of said memory cells in a column coupled between a pair of said bit lines, each of said memory cells including a pair of load transistors and a transistor means, each load transistor having a base and coupled between said first voltage terminal and said transistor means, said transistor means being further coupled to said one of said word lines and said pair of bit lines for storing said information in response to a signal on said bit lines, a plurality of first means, each of said first means coupled between said one of said word lines of each of said rows and said second voltage terminal for sinking current from said one of said word lines during said write mode and said read mode, said circuit comprising:

• a plurality of second means, each of said second means coupled between said one of said word lines of each of said rows and said second voltage terminal for sinking additional current from said one of said word lines during said write mode, said low current mode, and said read mode;
• and
• a plurality of third means, each of said third means coupled between a base of both of said pair of load transistors and said one of said word lines of each of said rows for selectively applying voltage to one of said word lines for selecting one of said word lines during said write modes and said read modes.