Semiconductor memories
AssigneeStc PLC
InventorDavid L. Waller
Life of this patent
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Abstract
A bit-line load for a static random access memory incorporates a load comprising a diode, and current limiting means in series with the diode, the diode/limiter assembly being shunted by a current source. This overcomes both the V.sub.dd drop problem and the high write cycle current flow experienced with conventional bit line loads.
Claims5
A static random access memory, including an array of memory cells, and a plurality of bit-lines whereby the cells are accessed to effect reading and writing of data, wherein each bit-line is provided with a load comprising a diode or diode equivalent, current limiting means in series with the diode, and a current source in parallel with the diode and limiting means.
Dependencies are inferred from the claim text.