On-chip programmability verification circuit for programmable read only memory having lateral fuses

A programmable memory circuit comprising:

• a plurality of word lines;
• a plurality of bit lines;
• a plurality of fuses, each of said fuses uniquely coupled between one of said word lines and one of said bit lines;
• first means coupled to said plurality of bit lines for selecting one of said bit lines;
• a first diode having a cathode coupled to one of said word lines and an anode;
• second means coupled to said anode of said first diode for selecting one of said word lines;
• an output terminal;
• a first supply voltage terminal;
• a second supply voltage terminal;
• third means coupled to said first and second supply voltage terminal and coupled between said anode of said first diode and said output terminal for sensing the voltage on one of said word lines and translating said voltage to one of said output terminals as an output signal;
• a first resistor;
• a second resistor;
• a test voltage terminal coupled for receiving a test voltage;
• a second diode having an anode coupled to said test voltage terminal and a cathode;
• and
• a transistor having a base coupled to said first supply voltage terminal by said first resistor and to said second means, an emitter coupled to said anode of said first diode, and a collector coupled to said anode of said second diode by said second resistor.