Audio delay system
AssigneeAnalog and Digital Systems, Inc.
InventorDaniel T. Sullivan
Life of this patent
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Abstract
Variably delaying an audio signal by storing digital representions of the audio signal at sequential memory locations prescribed by an encoding pointer operating at one clock rate, and reading from the memory at sequential locations prescribed by a decoding pointer operating at the same or a different clock rate, with the difference in clock rates between the pointers prescribing the rate of change of delay. A memory addressing system in which a processor specifies the high-order portion of a memory address and a separate counter, clocked at a much higher rate than the processor, provides the low-order portion of the address.
Claims11
A system for variably delaying an audio signal, said apparatus comprising
- memory means for storing a sequence of numbers comprising digital representions of consecutive portions of said audio signal,
- addressing means for generating encoding and decoding pointers for accessing said memory means,
- memory writing means for writing said numbers at sequential memory locations prescribed by said encoding pointer,
- memory reading means for reading numbers from said memory at sequential locations prescribed by said decoding pointer,
- clock means for generating encoding and decoding clock signals,
- said addressing means including means for incrementing said encoding pointer in response to said encoding clock and for incrementing said decoding pointer in response to said decoding clock, and for shifting said encoding and decoding pointers to a predetermined low address in said memory (e.g., the zero address) after a predetermined higher address (e.g., the highest address) is reached,
- means for varying the frequency of said decoding clock relative to said encoding clock, thereby to vary address separation between said encoding and decoding pointers and the amount of delay of said audio signal.
A memory addressing system comprising
- a processor for prescribing the high-order portion of a memory address,
- a counter for prescribing the low-order portion of said memory address,
- processor clock means for operating said processor at a processor clock rate,
- counter clock means for operating said counter at a counter clock rate, said counter clock rate being at least four times said processor clock rate,
- means for providing an overflow indication to said processor when said counter has overflowed,
- means for incrementing said high-order address portion in response to said overflow indication.
Dependencies are inferred from the claim text.