Logic full adder circuit

A logic full adder for adding two binary numbers a and b having n bits each, where n is equal to or greater than 2 including a plurality of single bit adders, each comprising:

• an inverting AND gate and inverting OR gate for receiving a pair of like bit numbers a.sub.i and b.sub.i and producing an inverted OR signal a.sub.i +b.sub.i and an inverted AND signal a.sub.i .multidot.b.sub.i for each of said pairs of bit numbers;
• a summing circuit for producing a sum signal from each pair of said like bit numbers a.sub.i and b.sub.i comprising a logic gate which receives said like bit numbers a.sub.i, b.sub.i and said inverted AND signal a.sub.i .multidot.b.sub.i, and forms on first and second outputs a first signal a.sub.i .multidot.b.sub.i .multidot.(a.sub.i +b.sub.i), and a second signal a.sub.i .multidot.b.sub.i .multidot.(a.sub.i +b.sub.i), respectively;
• a pair of electronic switches connected to receive said first and second signals, and operated in response to a carry signal c.sub.i, to supply either said first signal or said second signal to a first junction;
• and
• a carry look-ahead circuit for generating a carry look-ahead signal from said inverted OR signals a.sub.i +b.sub.i and said inverted AND signals a.sub.i .multidot.b.sub.i produced by each of said pairs of bit numbers.