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AssigneeU.S. Philips Corporation
InventorsLeendert J. Van De Polder, Leonard J. M. Esser
Estimating the term…
A color television Y/U/V luminance-chrominance multiplex signal with signals which may or may not be compressed in time comprises for a television line the associated luminance information Y and half the chrominance information U or V. As a result the circuit should supply the chrominance information directly (U, V) and repeatedly (U', V') during a subsequent television line. To avoid the use of an accurate, expensive delay device having a line period delay, the circuit includes an input shift register (A) of the series-in, parallel-out type, which is coupled through an on-off switch circuit (B1, B2) to parallel inputs of two shift registers (C1, C2) of the parallel-in, series-out type. During a line blanking period (THB) writing is effected from the input shift register in the output shift registers and during two subsequent line scan periods (THS1, THS2) reading is effected consecutively therefrom. Reading may be effected in opposite phase if a repetition is to be effected after exactly one line period.
A color television receiver having a converter circuit for converting a time division multiplex television signal into simultaneous signals, said time division multiplex signal having an interrupted sequence of a first information component relating to luminance information occurring in first periods, the first information components being separated by a further sequence of a second and a third information component relating to chrominance information occurring in second and third periods, respectively, said simultaneous signals corresponding to the first, second and third information components and repeated third and second information components, respectively, said second and third information components, either repeated or not, being expanded in time so that they occur in the simultaneous signals during the same first period or a fourth period, respectively, as the first information components when said first or fourth periods correspond to television line scan periods, the converter circuit including signal sampling, expansion and repetition means disposed between a circuit input and a circuit output for the second and third information components relating to chrominance information, said means being formed with shift registers having different write and read rates under the control of clock pulses of different clock pulse frequencies, characterized in that for the signal sampling, expansion and repetition means the said circuit input of the converter circuit is coupled to a signal input of at least one input shift register of the series-in, parallel-out type and that the said circuit output of the converter circuit with the expanded second and third information components relating to chrominance, repeated or not, is coupled to respective signal outputs of first and second output shift registers of the parallel-in, series-out type, parallel outputs of the input shift register being coupled through an on-off switch circuit to respective parallel inputs of the first and second output shift registers, said switch circuit being periodically conducting prior to the occurrence of the first and fourth periods during television line blanking periods and being non-conducting during the first or fourth television line scan periods, corresponding to the first and second output shift registers alternately applying per respective line scan period the second and third information components, and the repeated second and third information components, respectively, to the respective circuit output.
A color television receiver as claimed in any one of the preceding claims, wherein reading in the first register is effected in opposite phase to the reading in the second output shift register.
An integrated circuit suitable for use in a color television receiver having a converter circuit for converting a time division multiplex television signal into simultaneous signals, said time division multiplex signal having an interrupted sequence of a first information component relating to luminance information occurring in first periods, the first information components being separated by a further sequence of a second and a third information component relating to chrominance information occurring in second and third periods, respectively, said simultaneous signals corresponding to the first, second and third information components and repeated third and second information components, respectively, said second and third information components, either repeated or not, being expanded in time so that they occur in the simultaneous signals during the same first period or a fourth period, respectively, as the first information components when said first or fourth periods correspond to television line scan periods, the converter circuit including signal sampling, expansion and repetition means disposed between a circuit input and a circuit output for the second and third information components relating to chrominance information, said means being formed with shift registers having different write and read rates under the control of clock pulses of different clock pulse frequencies, wherein for the signal sampling, expansion and repetition means the said circuit input of the converter circuit is coupled to a signal input of at least one input shift register of the series-in, parallel-out type and that the said circuit output of the converter circuit with the expanded second and third information components relating to chrominance, repeated or not, is coupled to respective signal outputs of first and second output shift registers of the parallel-in, series-out type, parallel outputs of the input shift register being coupled through an on-off switch circuit to respective parallel inputs of the first and second output shift registers, said switch circuit being periodically conducting prior to the occurrence of the first and fourth periods during television line blanking periods and being non-conducting during the first or fourth television line sca periods, corresponding to the first and second output shift registers alternately applying per respective line scan period the second and third information components, and the repeated second and third information components, respectively, to the respective circuit output, said integral circuit comprising:
Dependencies are inferred from the claim text.