US 4,730,130 A · Writable array logic

Abstract

A bipolar writable array logic device is provided having an output representing a logical AND function and a logical OR function in response to a plurality of input signals. An AND matrix decode and an OR matrix decode are coupled to an input circuit for separately decoding a plurality of input signals. An array of collector sensed memory cells is coupled to the AND matrix decode for selecting desired rows of the collector sensed memory cells. A first plurality of sense amplifiers are coupled between the OR matrix decode and columns of the collector sensed memory cells for providing an ANDed output. Rows of an array of emitter sensed memory cells are coupled to the first plurality of sense amplifiers. A second plurality of sense amplifiers are coupled to columns of the emitter sensed memory cells for providing the bipolar writable array logic device output.

Claims18

Dependent claims

A bipolar writable array logic device providing a device output representing a logical AND function and a logical OR function in response to a plurality of input signals, said device comprising:

first means for receiving said plurality of input signals;
second means coupled to said first means for decoding said input signals;
third means coupled to said first means for decoding said input signals;
fourth means coupled to said second and third means for providing said logical AND function;
and
fifth means coupled to said fourth means for providing said logical OR function and providing said output, wherein said logical AND and logical OR function may be reprogrammed by said input signals.

3 more elements

A bipolar writable array logic device providing a device output representing a logical AND function and a logical OR function, said device comprising:

a plurality of input terminals, each of said input terminals receiving one of a plurality of input signals;
first means coupled to said input terminals for decoding said input signals and providing a plurality of first decode signals and a plurality of second decode signals;
second means coupled to said first means for providing said logical AND function, said second means comprising an array of collector sensed memory cells arranged in rows and columns, wherein specific rows may be selected by said plurality of first decode signals;
a first plurality of sense amplifiers coupled to both said first means and said second means, each of said first plurality of sense amplifiers coupled to one of said columns of collector sensed memory cells and to one of said plurality of second decode signals and having an ANDed output signal;
and
third means for providing said device output coupled to said first plurality of sense amplifiers for providing said logical OR function, said third means comprising an array of emitter sensed memory cells arranged in rows and columns, wherein specific rows may be selected by said ANDed output signals.

3 more elements

Dependencies are inferred from the claim text.

Writable array logic

Life of this patent

Writable array logic

Life of this patent

Abstract

Claims18