Temperature compensated high performance hysteresis buffer

Abstract

A hysteresis circuit is disclosed in which a first signal path, including a hysteresis feedback loop, is separate from a second signal path that is used to carry data. When the signal input to the hysteresis circuit (also referred to hereinafter as the "input signal") crosses a first preselected hysteresis reference of ("threshold") level, the hysteresis feedback loop, which includes threshold adjustment means, will cause a change in the threshold from the first preselected level to a second preselected level. This adjustment of threshold level will take place in parallel with the data being propagated to the output over said separate second signal path. A subsequent crossing of the second preselected threshold level by said input signal will cause the first threshold level to the reset and so on. According to the preferred embodiment of the invention, the threshold adjustment means included in said first signal path further includes a temperature compensation string, current switching means and means which act as an anti-hysteresis killer to speed up the operation of the hysteresis circuit. This novel combination is operative to assure a preselected minimum hysteresis window over the 210.degree. C. temperature range between -55.degree. C. and 155.degree. C., and renders the hysteresis circuit suitable for use in both military applications and other hostile environments. Furthermore, according to the preferred embodiment of the invention, the hysteresis cirucit has a PNP input stage to reduce I.sub.IL and accordingly improve the input chracteristics of the circuit, particularly fan-in. The circuit also features a low I.sub.CC and is designed to be self-compensating with respect to manufacturing disparities inherent in components used to fabricate the circuit itself.

Dependencies are inferred from the claim text.