Semiconductor memory device

A semiconductor memory device having a memory array with a plurality of memory cells arranged in a matrix of row and column lines wherein the memory cells are addressed by selecting row and column lines and where some of the memory cells may be defective;

• a row decoder for selecting a row line;
• a column decoder for selecting a column line, and a selected memory cell being connected between selected row and column lines;
• detect means for detecting a defective memory cell connected between selected row and column lines;
• and sense means for sensing the data of a detected defective memory cell;
• wherein said detect means comprises:
• row detect circuits connected to the output of said row decoder, said row detect circuits being programmed to detect a selected row line having a defective cell;
• column detect circuits connected to the output of said column decoder, said column detect circuits being programmed to detect a selected column line having a defective cell;
• means connected to said row and column detect circuits to receive the outputs thereof for detecting the selection of a defective memory cell based on the logic values of the outputs of said row and column detect circuits;
• and
• means connected to said sense means and said detect means to receive the outputs thereof and for inverting the logic value of the data sensed by said sense means based on the logic value of the output of said detect means.