Broadcast instruction for use in a high performance computer system

For use in a data processing system comprised of a plurality of processors, each one of said processors including an execution unit (46) and a memory (51), said processors being able to communicate with each other through a plurality of input and output ports (48), each output port including an output address pointer register (170) which points to locations in said memory (51) from which data are to be transferred, at least one of said processors including instruction decoding means (44) and an address unit (42) having access to said memory (51) over a memory interface (50), said memory (51) having stored therein a broadcast pointer instruction (400), said address unit (42), and said I/O ports being connected together by a common address bus (52) and a common data bus (54), said I/O ports having access to said memory (51) over said memory interface (50), a communication mechanism in said one processor comprising:

• means in said instruction decoder (44) for decoding said broadcast pointer instruction;
• said broadcast pointer instruction (400) including a first source operand, said first source operand being an address pointer value which is the starting address in said memory (51) of message data to be broadcast to a number of said processors through said ports (48);
• said broadcast pointer instruction (400) including a first destination operand, said first destination operand being a first multibit mask, there being at least one bit position in said first mask for each one of said plurality of output ports in said one processor;
• and,
• a first register (404, 402) for storing said first multibit mask (404) and said first source operand (402),
• said address unit (42) including first logic (406) connected to said first register (404, 402) and to said common address and data bus (52, 54) for placing on said data bus (54) said address pointer value (404) in said first source operand of said broadcast pointer instruction, and for sequentially placing on said address bus (54) the port number of each of said output ports whose numbers correspond to bit positions in said first mask register (402) that are set to be one, such that each output port that is designated in said first mask (404) receives said starting address of the message data in said memory (51), means in said output port for storing said starting address in said output address pointer register and for outputting said message data in said memory (51) to the processors identified in said broadcast pointer instruction (400) via said input port of the processors identified in said broadcast pointer instruction (400).