Digital circuit for steepening color-signal transitions
AssigneeDeutsche ITT Industries GmbH
InventorsPeter M. Flamm, Rolf Deubert
Life of this patent
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Abstract
This circuit arrangement is designed for use in digital color-television receivers or the like and contains for each of the two digital color-difference signals a slope detector to which both a digital signal defining an amplitude threshold value and a digital signal defining a time threshold value are applied. At least one intermediate value occurring during an edge to be steepened is stored, and at the same time value of the steepened edge, it is "inserted" into the latter. This is done by means of memories switches, output registers, and a sequence controller.
Claims4
A circuit arrangement for steepening color-signal transitions, comprising:
- first and second circuit branches, said first branch receiving a first color difference digital signal from a first color difference channel and said second branch receiving a second color difference digital signal from a second color difference channel, each of said branches comprising:
- a digital slope detector for generating a control signal at an output when the respective one of said first or second color difference digital signals has a predetermined relationship to predetermined amplitude and time thresholds;
- a first delay element receiving and delaying said respective one color difference digital signal by a time equal to the delay of said digital slope detector;
- at least one memory having its input connected to the output of said first delay element;
- a switch having first and second inputs connected to the outputs of said delay element and said at least one memory, respectively;
- and
- an output register having its input connected to the output of said switch;
- and
- a sequence controller coupled to the outputs of said digital slope detectors in said first and second circuit branches, and receiving a clock signal having a predetermined frequency relationship to a chrominance subcarrier frequency, and receiving a digital signal determining the hold time equal to the known system rise time of said first and second color difference channels, said sequence controller providing sequence control signals for controlling said at least one memory, said switch and said output register in both of said first and second circuit branches such that:
- a color difference signal value occurring at an intermediate value of said hold time is read into said memory, said color difference signal value stored in said memory is read via said switch into said output rergister at the corresponding intermediate value of the steepened leading edge of said color-signal, the input of said output register being connected to the output of said delay element at all times except at said intermediate value of said steepened leading edge.
Dependencies are inferred from the claim text.