Self-aligned sidewall gate IGFET

A semiconductor device comprising:

• a semiconductor substrate of a first conductivity type;
• a layer member formed in a predetermined pattern on the major surface of the semiconductor substrate and having a first insulating side surface;
• a first insulating layer formed on the major surface of the semiconductor substrate and extending from the first insulating side surface of the layer member;
• a first conductive layer formed on the first insulating layer in contact with the first insulating side surface of the layer member, said first conductive layer having a marginal edge extending upwardly from said first insulating layer, and said first conductive layer having a length which extends substantially parallel to said first insulating side surface and a width which extends in a direction substantially perpendicular to said first insulating side surface, said width extending only from said marginal edge to said first insulating side surface;
• a first semiconductor region of a second conductivity type reverse from the first conductivity type, formed in the semiconductor substrate from the side of its major surface and having a marginal edge extending downwardly from the major surface such that the latter marginal edge is substantially aligned with the marginal edge of the first conductive layer, the first semiconductor region extending from its marginal edge away from the first conductive layer;
• a second semiconductor region of the second conductivity type formed in the semiconductor substrate from the side of its major surface to underlie the layer member in contact therewith, the second semiconductor region having a marginal edge extending downwardly from the major surface such that the marginal edge of said second semiconductor region is substantially aligned with the first insulating side surface of the layer member, the second semiconductor region extending from its marginal edge away from the first conductive layer;
• wherein a first insulated gate field effect transistor is constituted using the first conductive layer as its gate electrode, that region of the first insulating layer underlying the gate electrode as its gate insulating layer, the first semiconductor region as either one of its source and drain regions, the second semiconductor region as the other of its source and drain regions.