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US 4,729,000 AGranted
Low power AlGaAs/GaAs complementary FETs incorporating InGaAs n-channel gates
AssigneeHoneywell Inc.
InventorJonathan K. Abrokwah
Life of this patent
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Abstract
A low power complementary (Al,Ga)As/GaAs heterostructure insulated gate field-effect transistor (HIGFET) approach is described in which the n-channel transistor utilizes an In.sub.x Ga.sub.1-x As semiconductor gate to reduce threshold voltage (V.sub.t) of the n-channel FET to allow low power circuit operation.
Claims15
A lower planar complementary GaAs based heterostructure integrated circuit structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising
- a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a heavily doped In.sub.y Ga.sub.1-y As (where 0<y<0.2) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers;
- a n.sup.+ source and a n.sup.+ drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al-Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a MBE grown thin-layer of heavily doped In.sub.y Ga.sub.1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode;
- a first metal gate electrode deposited on the surface of the In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
8 more elements
A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a third epitaxially grown layer of intrinsic GaAs over said second layer;
- a fourth epitaxially grown area of highly doped In.sub.y Ga.sub.1-y As on said third layer and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said third epitaxial layer;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising
- a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a heavily doped In.sub.y Ga.sub.1-y As (where 0<y<0.2) thin layer of a thickness of less than about 1000 .ANG. epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers;
- a n.sup.+ source and a n.sup.+ drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising
- a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a heavily doped In.sub.y Ga.sub.1-y As (where y is a fraction on the order of 0.15) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers;
- a n.sup.+ source and a n.sup.+ drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain region, respectively.
9 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- planar epitaxial grown intrinsic layers sequentially grown in order over said flat major surface comprising
- a first epitaxially grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As grown directly over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a heavily doped In.sub.y Ga.sub.1-y As (where 0<y<0.2) thin layer epitaxially grown on the final layer of said intrinsic layers and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1- As;
- a second metal gate electrode deposited on the surface of the final layer of said intrinsic layers, in which said first and second metal gate electrodes are of WSi;
- a n.sup.+ source and a n.sup.+ drain region in said structure defined by selective donor ion implantation into said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region in said structure defined by selective acceptor ion implantation into said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAS heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which th energy gap difference is divided between valence and conduction bands;
- a MBE grown thin-layer of heavily doped In.sub.y Ga.sub.1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode in which said heavily doped epitaxial layer of In.sub.y Ga.sub.1-y As is of a thickness in the range of 200 to 500 .ANG.;
- a first metal gate electrode deposited on the surface of the In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
8 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-alinged gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a MBE grown thin-layer of heavily doped In.sub.y Ga.sub.1-y As (where y is a fraction on the order of 0.15) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode;
- a first metal gate electrode deposited on the surface of the In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer;
- a n.sup.+ and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
8 more elements
A low-power planar complementary GaAs based heterostructure integrated circuit structure having complementary self-aligned gate (Al,Ga)As/GaAs heterostructure devices with an insulating (Al,Ga)As (SAG) gate structure to form CMOS-like GaAs IC's, the planar complementary IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first MBE grown layer of intrinsic GaAs grown directly over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second MBE grown layer of intrinsic (Al,Ga)As grown directly over said layer of i-GaAs, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a MBE grown thin-layer of heavily doped IN.sub.y Ga.sub.1-y As (where 0<y<0.2) on the layer of i-(Al,Ga)As and defining the location of a first gate electrode;
- a first metal gate electrode deposited on the surface of the In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said i-(Al,Ga)As layer, in which said first and second metal gate electrodes are of WSi;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
8 more elements
A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second eptixially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a third epitaxially grown layer of intrinsic GaAs over said second layer;
- a fourth epitaxially grown area of highly doped In.sub.y Ga.sub.1-y As on said third layer and defining the location of a first gate electrode, in which said highly doped layer of In.sub.y Ga.sub.1-y As is of a thickness of less than about 1000 .ANG.;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said third epitaxially layer;
- a n.sup.+ and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a third epitaxially grown layer of intrinsic GaAs over said second layer;
- a fourth epitaxially grown area of highly doped In.sub.y Ga.sub.1-y As on said third layer and defining the location of a first gate electrode, in which y is a fraction on the order of 0.15;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said third epitaxially layer;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
A complementary, planar heterostructure IC in which both the n-channel and p-channel transistors utilize a 2D electron (hole) gas in an undoped high mobility channel to form CMOS-like IC's, the complementary, planar IC structure comprising:
- semi-insulating GaAs substrate means having a flat major surface;
- a first epitaxially grown layer of intrinsic GaAs over said surface, said GaAs layer having high mobility and having a first bandgap;
- a second epitaxially grown layer of intrinsic (Al,Ga)As over said first layer, which i-(Al,Ga)As has a larger bandgap than said first bandgap, and in which the energy gap difference is divided between valence and conduction bands;
- a third epitaxially grown layer of intrinsic GaAS over said second layer;
- a fourth epitaxially grown area of highly doped In.sub.y Ga.sub.1-y As on said third layer and defining the location of a first gate electrode;
- a first metal gate electrode deposited on said In.sub.y Ga.sub.1-y As;
- a second metal gate electrode deposited on the surface of said third epitaxial layer, in which said first and second metal gate electrodes are of WSi;
- a n.sup.+ source and a n.sup.+ drain region defined by selective donor ion implantation in said structure next to said first gate electrode;
- a p.sup.+ source and a p.sup.+ drain region defined by selective acceptor ion implantation in said structure next to said second gate electrode;
- first and second n-ohmic contacts alloyed to said n-source and n-drain regions, respectively;
- and,
- third and fourth p-ohmic contacts alloyed to said p-source and p-drain regions, respectively.
9 more elements
Dependencies are inferred from the claim text.