Timer circuit
AssigneeKabushiki Kaisha Toshiba
InventorJun-ichi Tsujimoto
Life of this patent
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Abstract
A timer circuit which is used for write and erase time control of a semicondcutor memory, and configured so as to transfer a charge of a charge storage capacitor to a charge pump capacitor through a first transfer gate thereafter to repeatedly effect a discharge operation by using a second transfer gate thereby to gradually reduce a charge of the charge storage capacitor, thus performing a timer operation, characterized in that there is provided a circuit for making an adjustment such that a voltage applied to the charge pump capacitor is smaller than a voltage applied to the charge storage capacitor.
Claims5
A timer circuit comprising:
- (a) a charge storage capacitor having a first terminal and a second terminal connected to ground;
- (b) a charge pumping capacitor having a first terminal and a second terminal;
- (c) a first transistor means for connecting the first terminal of said charge storage capacitor to a power supply when a reset signal is applied thereto;
- (d) a second transistor means coupled serially between said second terminal of said charge pumping capacitor and ground to keep the potential at said second terminal higher than ground potential by an amount of voltage drop of said second transistor means;
- (e) a first transfer gate means connected between the first terminals of said charge storage and charge pumping capacitors to periodically transfer a part of a charge stored in said charge storage capacitor to said charge pumping capacitor according to one phase signal of a two-phase clock after application of said reset signal;
- (f) a second transfer gate means connected to said second terminal of said charge pumping capacitor to periodically discharge a charge stored in said charge pumping capacitor according to another phase signal of the two-phase clock after application of said reset signal;
- and
- (g) an adjustment circuit including at least one adjusting transistor means which has a low back-bias effect, connected to said charge storage capacitor to control the potential of the stored charge of said charge storage capacitor within a range determined by a threshold voltage of said adjusting transistor means from the potential of the second terminal of said charge pumping capacitor.
Dependencies are inferred from the claim text.