Static PLA or ROM circuit with self-generated precharge

A static PLA circuit comprising:

• logic gate means having inputs for receiving input select signals and an output;
• a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said logic gate means;
• and
• feedback means connected between the output of said logic gate means and the gate of said precharge MOS transistor for delaying the turn-on time of said MOS transistor when the output of said logic gate means is making a high-to-low transition in response to said input select signals and for delaying the turn-off time of said MOS transistor when the output of said logic gate means is making a low-to-high transition in response to said input select signals.

A static PLA circuit comprising:

• a NOR logic gate having inputs for receiving input select signals and having an output;
• a precharge MOS transistor having one of its main electrodes connected to a supply potential and its other main electrode connected to the output of said NOR gate;
• said precharge MOS transistor being formed of a P-channel transistor;
• a feedback circuit portion formed of inverter means connected between the output of said NOR gate and the gate of said precharge MOS transistor;
• said inverter means including a first inverter and a second inverter, said first inverter having its input connected to the output of said NOR gate and its output connected to the input of said second inverter, said second inverter having its output connected to the gate of said P-channel transistor;
• and
• said P-channel transistor being delayed in its turn-on time by said first and second inverters when the output of said NOR gate is making a high-to-low transition.