A logic circuit on a substrate switchable between a test mode and an operational mode, said substrate having a surface layer with n-type and p-type regions formed therein comprising:
- first and second input terminals;
- first and second output terminals;
- a control input;
- a V.sub.DD terminal;
- a V.sub.SS terminal;
- a first NOR gate including:
- a first transistor formed by a first p-type region on said substrate and a first conductive layer insulatedly disposed over said first p-type region, an input of said first transistor being coupled to said V.sub.DD terminal, a gate electrode of said first transistor being formed by said first conductive layer which is coupled to said first input terminal;
- a second transistor formed by said first p-type region and a second conductive layer insulatedly disposed over said first p-type region, an output of said second transistor being coupled to said first output terminal, a gate electrode of said second transistor being formed by said second conductive layer;
- a third transistor formed by a first n-type region on said substrate and said first conductive layer insulatedly disposed over said first n-type region, an output of said third transistor being coupled to said first output terminal, an input of said third transistor being coupled to said V.sub.SS terminal, a gate electrode of said third transistor being formed by said first conductive layer;
- and
- a fourth transistor formed by said first n-type region and said second conductive layer insulatedly disposed over said first n-type region, an output of said fourth transistor being coupled to said first output terminal, an input of said fourth transistor being coupled to said V.sub.SS terminal, a gate electrode of said fourth transistor being formed by said second conductive layer;
- a second NOR gate including:
- a fifth transistor formed by a second p-type region on said substrate and a third conductive layer insulatedly disposed on said second p-type region, an output of said fifth transistor being coupled to said second output terminal, a gate electrode of said fifth transistor being formed by said third conductive layer;
- a sixth transistor formed by said second p-type region and a fourth conductive layer insulatedly disposed over said second p-type region, an output of said sixth transistor being coupled to said V.sub.DD terminal, a gate electrode of said sixth transistor being formed by said fourth conductive layer which is coupled to said second input terminal;
- a seventh transistor formed by a second n-type region on said substrate and said third conductive layer insulatedly disposed over said second n-type region, an input of said seventh transistor being coupled to said V.sub.SS terminal, an output of said seventh transistor being coupled to said second output terminal, a gate electrode of said seventh transistor being formed by said third conductive layer;
- and
- an eighth transistor formed by said second n-type region and said fourth conductive layer insulatedly disposed over said second n-type region, an input of said eighth transistor being coupled to said V.sub.SS terminal, an output of said eighth transistor being coupled to said second output terminal, a gate electrode of said eighth transistor being formed by said fourth conductive layer;
- first transfer gate means for selectively cross-coupling and separating said first and second NOR gates in response to a control signal input through said control input, said first transfer gate means being located on said substrate between said first and second p-type regions and having an output coupled to said second conductive layer, an input coupled to the output of said fifth transistor, and a gate electrode coupled to said control input, said first transfer gate means output being coupled to said gate electrode of said second transistor by a first metal connection;
- second transfer gate means for selectively cross-coupling and separating said first and second NOR gates in response to said control signal input through said control input, said second transfer gate means located on said substrate between said first and second n-type regions and having an output coupled to said third conductive layer, an input coupled to the output of said second transistor, and a gate electrode coupled to said control input, said second transfer gate means being coupled to said gate electrode from said fifth transistor by a second metal connection, said first and second metal connections each having a length selected to reduce capacitance between said each metal connection and said substrate, said control input receiving a signal whose timing is selected to permit natural discharge of said second and fifth transistors.