Error and calibration pulse generator

An electronic circuit for selectively generating first and second output pulses which differ in duration by a predetermined amount, said circuit having a clock terminal for receiving clock transitions at precisely determined intervals and comprising:

• a first sequential logic device having a data input terminal, a clock input terminal, and first and second complementary output terminals, said first sequential logic device having a first state in which the first and second output terminals are at first and second binary logic output levels respectively and a second state in which the first and second output terminals are at said second and first binary logic output levels respectively, and said first sequential logic device being placed in its first state when a clock transition is received at the clock input terminal while the data input terminal is at a first of two binary logic input levels and being placed in its second state when a clock transition is received at the clock input terminal while the data input terminal is at the second of said two binary logic input levels,
• a second sequential logic device having a data input terminal, a clock input terminal, and at least one output terminal, said second sequential logic device having a first state in which the output terminal is at one of said first and second binary logic output levels and a second state in which the output terminal is at the other of said first and second binary logic output levels, and said second sequential logic device being placed in its first state when a clock transition is received at the clock input terminal while the data input terminal is at one of said first and second binary logic input levels and being placed in its second state when a clock transition is received at the clock input terminal while the data input terminal is at the other of said first and second binary logic input levels,
• a combinational logic device having a first input terminal coupled to one of the first and second output terminals of the first sequential logic device, a second input terminal coupled to the output terminal of the second sequential logic device, and an output terminal,
• means coupling the clock terminal of the circuit to the clock input terminals of the first and second sequential logic devices and coupling the other of the first and second output terminals of the first sequential logic device to the data input terminal of the second sequential logic device, and
• control means for selectively placing the coupling means in a first state such that the binary logic output level present at said other output terminal of the first sequential logic device is propagated to the data input terminal of the second sequential logic device by a first predetermined number of clock transitions and the combinational logic device generates said first output pulse at its output terminal, or in a second state such that the binary logic output level present at said other output terminal of the first sequential logic device is propagated to the data input terminal of the second sequential logic device by a second predetermined number of clock transitions, said second number being different from said first number, and the combinational logic device generates said second output pulse, having a different duration from said first output pulse, at its output terminal.