Sample-and-hold circuit

#The present invention relates to a sample-and-hold circuit for sampling and holding the output signals of an A/D converter used in communications systems, audio systems, video systems and the like.

#Such a sample-and-hold circuit is disclosed in Rudy J. Van de Plassche, et al. A Monolithic High-Speed Sample-and-Hold Amplifier for Digital Audio in IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 6, December 1983, p. 717 (FIG. 1). FIG. 1 shows the structure of this circuit. In this sample-and-hold circuit, an input signal V.sub.IN is supplied to the non-inverting input terminal (+) of operational amplifier 11 through resistor R1 and switch S1. The output of operational amplifier 11 is fed back to the inverting input terminal (-) of amplifier 11. It is also supplied to the inverting input terminal (-) of operational amplifier 12 through switch S3. The non-inverting input terminal (+) of operational amplifier 12 is grounded. The output of amplifier 12 is fed back to the inverting input terminal (-) of amplifier 12 through holding capacitor C.sub.H. It is also supplied to node N1 of resistor R1 and switch S2 through resistor R2. Switch S2 is connected between node N1 and the ground. Switches S1, S2 and S3 are selectively turned on and off, thereby controlling the operation of sampling and holding input signal V.sub.IN and thus obtaining output signal V.sub.OUT at the output terminal of operational amplifier 12.

#In the sample-and-hold circuit (SHC) of FIG. 1, an imaginary short-circuit occurs when switches S1 and S3 are simultaneously turned on. Potentials V1, V2 and V3 of node N1, node N2 (i.e., the output terminal of amplifier 11) and node N3 (i.e., the non-inverting input terminal of amplifier 12) thereby fall to the ground level. As a result, output signal V.sub.OUT becomes -V.sub.IN. In other words, an inverse of input signal V.sub.IN is obtained at the output terminal of operational amplifier 12. When switches S1 and S3 are turned off and switch S2 is turned on, holding capacitor C.sub.H maintains the output of operational amplifier 12 at a level attained in the previous sampling cycle. Since switch S2 is on, potential V1 of node N1 is reliably held at the ground level.

#FIG. 1 is a circuit diagram of a conventional sample-and-hold circuit;

#FIG. 2 shows the conventional electrical connection between a D/A converter and a sample-and-hold circuit;

#FIG. 3 is a block diagram of the sample-and-hold circuit according to a first embodiment of this invention;

#FIG. 3 is a block diagram showing the sample-and-hold hold circuit according to an embodiment of the present invention. This circuit has switched capacitor 15 for receiving the output signal of a D/A converter. The output of switched capacitor 15 is supplied to the input terminal of an amplifier 17 through impedance converter 16 and switch S5. The output of amplifier 17 is fed back to the input terminal of amplifier 17 through holding capacitor C.sub.H, and is also supplied to the input terminal of impedance converter 16 through switched capacitor 18.

#The voltage gain (V.sub.OUT /V.sub.IN) of this sample-and-hold circuit (FIG. 3) is determined by the two switched capacitors 15 and 18. The sample-and-hold circuit is set to the sample mode when switch S5 is closed, and amplifier 17 generates output signal V.sub.OUT which is exactly an inverse to input signal V.sub.IN as long as the voltage gain is -1. On the other hand, the sample-and-hold circuit set to the hold mode when switch S5 is opened, and holding capacitor C.sub.H maintains the level of output signal V.sub.OUT, which has been obtained in the preceding sampling cycle.

#As mentioned above, in the sample-and-hold circuit of FIG. 1, it is necessary to raise the input resistance (R). In contrast, the input resistance of the sample-and-hold circuit of FIG. 3 is indefinitely high since the input impedance is basically equal to capacitance C.sub.IN as is illustrated in FIG. 4. Therefore, it suffices to take only this input capacitance (C.sub.IN) into consideration. Hence, the sample-and-hold circuit of FIG. 3 can prevent the attenuation of an input signal, without increasing the pattern area, even if the input signal is the output of a high output-impedance D/A converter such as a D/A converter of charge-redistribution type. The sample-and-hold circuit can, therefore, be applied to various uses.