Self-aligned transistor method

A process for forming a bipolar transistor having an emitter, a base, a collector, and laterally surrounding isolation wall, wherein said isolation wall, emitter and emitter contact, base contact, and collector contact are self-aligned by a single master mask pattern, comprising:

• providing a semiconductor substrate having a principal surface;
• forming first and second superposed dielectric layers on said principal surface, wherein said first and second dielectric layers are differentially etchable with respect to each other and said substrate;
• using said single master mask pattern, forming openings in said first and second dielectric layers penetrating to said substrate and comprising at least a first opening for said emitter and emitter contact, a second opening for said base contact, a third opening for said collector contact, and a fourth opening for said isolation wall;
• forming opposed first sidewall liners of a third dielectric in said first through fourth openings, wherein said third dielectric is differentially etchable with respect to said substrate and said first dielectric layer and protects edges of said first layer exposed in said first through fourth openings;
• filling the space remaining between said opposed first sidewall liners in said first through fourth openings with a fourth dielectric different than said third dielectric and differentially etchable with respect to said third dielectric and said substrate;
• removing said fourth dielectric from said fourth opening and etching the portion of said substrate thereby exposed to form a trench in said substrate beneath said fourth opening;
• forming opposed second sidewall liners of a fifth dielectric at least on the sidewalls of said trench;
• filling the space remaining between said opposed second sidewall liners in said trench with polycrystalline semiconductor having an upper surface approximately level with said principal surface of said substrate;
• forming a sixth dielectric on said upper surface of said polycrystalline semiconductor;
• using a block-out mask, selectively removing said fourth dielectric from said first through third openings;
• anytime prior to the following steps, implanting said base region laterally encompassing said first and second openings;
• using a further block-out mask for selecting said first and third openings, implanting said emitter and emitter contact and said collector contact in said substrate beneath said first and third openings, respectively;
• and
• after said step of selectively removing said fourth dielectric from said first through third openings, using a still further block-out mask for selecting said second opening, implanting said base contact in said base region beneath said second opening.

A process for forming a semiconductor device having first, second, third, and fourth self-aligned regions in a substrate, comprising:

• providing said substrate having a principal surface;
• forming first and second dielectric layers on said principal surface, wherein said first and second dielectric layers are differentially etchable with respect to each other and said substrate;
• using a single mask pattern, etching first, second, third, and fourth openings through said first and second dielectric layers to said substrate, to locate respectively said first, second, third, and fourth regions in said substrate;
• providing first dielectric sidewall liners in said first through fourth openings, wherein said first dielectric sidewall liners are differentially etchable with respect to said first dielectric and said substrate;
• filling the space remaining in said first through fourth openings with a third dielectric differentially etchable with respect to said first sidewall liners and said substrate;
• removing said third dielectric from said fourth opening;
• etching said fourth region of said substrate beneath said fourth opening to form a trench in said substrate;
• providing second dielectric sidewall liners in said trench;
• filling the space remaining between said second sidewall liners in said trench with a polycrystalline semiconductor;
• doping a fifth region of said substrate encompassing said first and second regions with a dopant of a first conductivity type, and then in either order and without using a mask having an opening whose edge is laterally within said first, second, or third openings,
• doping said first and third regions of said substrate with a dopant of a second type opposite said first type through said first and third openings, and
• doping said second region of said substrate with a dopant of said first type through said second opening.