Method and apparatus for extracting a predetermined bit pattern from a serial bit stream

A method for locating the position of the framing pattern in a T1 serial bit stream encoded according to the ESF standard comprising the steps of:

• (a) providing a storage device capable of writing and reading 772 bits of data in sequence;
• (b) providing a counter;
• (c) writing a first state into all 772 bits of said storage device and selecting a first bit to address;
• (d) resetting said counter to a base count position;
• (e) upon the arrival of a bit of said serial bit stream taking 4 samples P.sub.1, P.sub.2,P.sub.3 and P.sub.4 of said serial bit stream where P.sub.1 is the last bit to have arrived, P.sub.2 is the bit stream taking 4 samples p.sub.1, P.sub.2, P.sub.s and P.sub.4, of said serial bit of said serial bit stream which arrived 772 bits prior to said P.sub.1 bit, P.sub.3 is the bit of said serial bit stream which arrived 772 bits prior to said P.sub.2 bit, and P.sub.4 is the bit which arrived 772 bits prior to said P.sub.3 bit;
• (f) determining if the bit pattern sequence P.sub.4, P.sub.3, P.sub.2 and P.sub.1 matches the any of the bit sequences 0010, 0101, 1011, 0110, 1100 and 1001;
• (g) if a match occurs, then incrementing said counter, and if a match does not occur, writing a second state into the bit currently addressed in said storage device;
• (h) incrementing the address of said storage device;
• (i) repeating steps (e) through (h) for 771 times;
• and
• (j) examining the state of said counter and repeating steps (c) through (j) if said counter is at said base count, repeating steps (d) through (j) if said counter has been incremented two or more times, and the position of said framing pattern having been located if said counter has been incremented only once.

Apparatus for locating the position of an N bit framing pattern in a serial bit stream wherein each of said framing bits is separated by P-1 bits of data, comprising:

• (a) first input terminal for receiving said serial bit stream;
• (b) first storage means for storing (M-1) X P bits of said serial bit stream coupled to said input terminal, where M is less than P and for providing at M-1 output terminals of said first storage means outputs constituting the P, 2P, . . . (M-1)P previous bits of said serial bit stream;
• (c) second storage means for storing binary numbers in P storage locations and for sequentially addressing each of said storage locations in synchronization with the arrival of said serial bit stream at said first input terminal, all of said storage locations of said second storage means being initially set to a first logic state;
• and
• (d) comparison means coupled to said first storage means and to said second storage means for determining if the bit of said serial bit stream present at said input terminal in combination with the P, 2P, . . . (M-1)P previous bits of said serial bit stream match any M sequences of the pattern formed by concatenating two of said framing bit patterns and for setting the storage location of said second storage means presently being addressed to a second logic state if a match does not occur and leaving undisturbed said storage location presently being addressed if a match occurs, the bit of said serial bit stream presently at said input terminal being a framing bit if the storage location of said second storage means presently addressed is the only one of said storage locations of said second storage means which is presently at said first logic state.

Apparatus for locating the position of the framing bits in a serial bit stream formed according to the ESF standard, comprising:

• (a) an input terminal for receiving said serial bit stream;
• (b) a 2,316 bit shift register coupled to said input terminal and clocked in synchronization with said serial bit stream such that said serial bit stream passes through said shift register, said shift register having first, second and third outputs at the 772nd, 1,544th and 2,316th bit positions respectively:
• (c) a decoder circuit coupled to said 2,316 bit shift register for determining if the bit present at said third output, said second output, said first output and said input terminal respectively match any of the bit patterns 0010, 0101, 1011, 0110, 1100 and 1001;
• (d) a 772 bit shift register coupled to said decoder circuit in which all bits of said 772 bit shift register are initially set to a first logic state and in which the bits recirculate through said 772 bit shift register in synchronization, and in which the bit at a single location is set to a second logic state if a match does not occur in said decoder circuit, the bit of said serial bit stream presently at said input terminal being a framing bit if the bit at said single location is the only one of said storage locations of said 772 bit shift register which is at said first logic state.