US 4,727,548 A · On-line, limited mode, built-in fault detection/isolation system for state machines and combinational logic

Abstract

A mechanism for the testing of digital signal processing circuitry (state machines and combinational logic) is built-in and continuously on-line with the system being tested. The operation of the signal processing architecture is monitored dynamically, namely across state transitions, employing a parity prediction operator which predicts the parity that should be produced by combining the contents of selected inputs and outputs of the architecture prior to and subsequent to a signal processing transition. If, due to a single bit failure, the predicted parity is not achieved, the output of an error detector will indicate a state other than that corresponding to the predicted parity and thereby report an error. To ensure accurate operation of the error reporting mechanism, the error signal is modulated by a clock signal the frequency of which is relatively low compared with the system clock that controls state transitions. The detection of interconnect wiring faults (e.g. among state machines) is accomplished by executing an exclusive-OR modulation of the digital signals with a prescribed clock signal the frequency of which is lower than the highest signal level transition rate expected on a communication link upstream of transmission over the link whose continuity is being tested. At the downstream end of the link, immediately adjacent entry into the state machine, the link is coupled to an activity detector. If the activity detector fails to detect change of state activity (i.e. the modulating clock) during a prescribed time window, a fault on the link is declared.

Claims36

Dependent claims

For use with a digital signal processing circuit having an input link to which at least one input signal is applied and an output link from which at least one output signal, characteristics of which depend upon the operation of said signal processing circuit with respect to signals applied to said input link, is derived, said at least one output signal being selectively fed back over a feedback link to be combined with said at least one input signal and applied to said input link, an arrangement for testing the operation of said signal processing circuit comprising:

first means, coupled to said input and output links, for generating a control signal which, when selectively combined with said at least one input signal and said at least one output signal derived from said signal processing circuit for an i.sup.th signal processing state and for an (i+1).sup.th signal processing state thereof, produces a first prescribed output signal in the absence of an error in the operation of said signal processing circuit;
and
second means, coupled to said input and output links and to said first means, for selectively combining said control signal, said at least one input signal and said at least one output signal derived from said signal processing circuit for said i.sup.th signal processing state and said at least one output signal derived from said signal processing circuit for said (i+1).sup.th signal processing state and producing said first prescribed output signal in the absence of an error in the operation of said signal processing circuit and producing a second prescribed output signal in response to the occurrence of an error in the operation of said signal processing circuit.

For use in a digital signal processing system wherein digital signals are coupled between respective portions of said system by way of signalling communication links, an arrangement for monitoring the transmission continuity of said communication links comprising:

first means, disposed at an upstream portion of a respective communication link, for modulating digital signals coupled thereto at a prescribed frequency lower than the rate of change of the state of said digital signals;
and
second means, disposed at a downstream portion of said respective communication link, for monitoring said link for the presence of modulating activity for a prescribed measurement interval and, upon failing to detect the presence of modulation activity thereat, generating an output signal representative of the loss of transmission continuity of said link.

For use with a digital signal processing circuit having an input link to which at least one input signal is applied and an output link from which at least one output signal, characteristics of which depend upon the operation of said signal processing circuit with respect to signals applied to said input link, is derived, said at least one output signal being selectively applied to a feedback link to be combined with said at least one input signal and applied to said input link, an arrangement for testing the operation of said signal processing circuit comprising:

first means for generating a control signal which, when selectively combined with said at least one input signal and said at least one output signal derived from said signal processing circuit for a first signal processing state and for an subsequent signal processing state thereof, produces a first prescribed output signal in the absence of an error in the operation of said signal processing circuit;
and
second means, coupled to said input and output links and to said first means, for selectively combining said control signal, said at least one input signal and said at least one output signal derived from said signal processing circuit for said first signal processing state and said at least one output signal derived from said signal processing circuit for said subsequent signal processing state and producing said first prescribed output signal in the absence of an error in the operation of said signal processing circuit and producing an second prescribed output signal in response to the occurrence of an error in the operation of said signal processing circuit.

Dependencies are inferred from the claim text.

On-line, limited mode, built-in fault detection/isolation system for state machines and combinational logic

Life of this patent

On-line, limited mode, built-in fault detection/isolation system for state machines and combinational logic

Life of this patent

Abstract

Claims36