Method and apparatus for isolating faults in a digital logic circuit

A method of generating a list of circuit elements for use in isolating faults in a logic circuit, the logic circuit having a plurality of circuit elements and a plurality of test points at the outputs of predetermined ones of the circuit elements, the circuit elements interconnected in successive stages to form a plurality of signal paths extending upstream from the test points, the logic circuit performing operations in accordance with a plurality of successive clock cycles, the method comprising the steps of:

• (a) simulating the execution of a diagnostic procedure on the logic circuit to perform a predetermined operation of the logic circuit using a logic model including simulated circuit elements and simulated test points corresponding to the logic circuit elements and logic circuit test points;
• (b) storing the logic states of the simulated test points at a plurality of clock cycles during the simulated execution of the diagnostic procedure;
• (c) specifying subsets of the stored logic states as seed signals at which a malfunction of the predetermined operation can be detected;
• (e) examining the simulated circuit elements generating each seed signal to identify signal paths being supplied as inputs to the examined simulated circuit elements;
• (f) evaluating the simulated circuit elements generating the seed signals based on predetermined criteria to eliminate signal paths and simulated circuit elements thereof which are incapable of causing the malfunction indicated by the seed signals;
• (g) recursively evaluating the simulated circuit elements of successive upstream stages of non-eliminated signal paths and simulated circuit elements thereof according to the predetermined criteria;
• and
• (h) storing the non-eliminated circuit elements as candidates capable of causing the malfunctions.