An apparatus for performing a remote signalling method for a digital transmission link, said method comprising transmitting the signalling by means of a digital message at the same rate as the digital data stream conveyed by the link, which message momentarily takes the place of said digital data stream, wherein said digital message is constitute by not more than n identical and non-consecutive sequences of N bits, where n and N are integers greater than 1, which sequences succeed one another in n successive time intervals of duration T with each sequence constituted by a periodic configuration of bits obtained by repeating a pattern, the first sequence being present whenever a message is sent, and the presence or absence of the other sequences during the following n-1 time intervals representing the values 0 or 1 of the n-1 digits of a binary number encoding remote signalling data, the presence of said patterns being recognized by identifying p patterns from a string of q.multidot.u successive bits in the digital stream conveyed by the link, where p and u are integers greater than 1, and q is the number of bits in a pattern, said apparatus including at least one equipment provided with a circuit for exploiting said signalling and with a circuit for recovering the bit rate from the digital stream, said apparatus including at least one receiving circuit for receiving remote signalling messages, said circuit being located in said equipment and being constituted by a circuit for recognizing p patterns from q.multidot.u successive bits in the digital stream conveyed by the link, together with a sampling circuit connected to store samples at the sequence succession rate (1/T), said circuit for recognizing p patterns from q.multidot.u successive bit patterns comprising:
- a serial-input/parallel-output shift register connected to receive the digital stream conveyed by the link and clocked by the clock signal generated by said bit rate recovery circuit, and delivering binary words having the same length as a pattern at its parallel output;
- a comparator for comparing two binary numbers having the length of a pattern, one of said binary numbers being identical to a pattern and being hardwired, and the other of said binary numbers being the number delivered by the parallel output from the shift register;
- a pattern rate generator constituted by divider driven by the clock signal generated by the bit rate recovery circuit;
- a u counter driven by the output signal from the pattern rate generator and marking strings of q.multidot.u successive bits in the digital stream;
- a coincidence detector connected to the output from said comparator and connected to be reinitialized at the pattern succession rate by the pattern rate generator:
- a p counter driven by the output signal from said coincidence detector;
- and
- a trigger circuit which is connected to be activated by said comparator and to be reset to zero by said u counter, and which, while it is reset to zero, inhibits said pattern rate generator and maintains said p and u counters in their zero states.