Apparatus for limiting minority carrier injection in CMOS memories
AssigneeIntel Corporation
InventorPaul D. Madland
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Abstract
A CMOS array is described where the memory cells are formed in n-type wells. No back biasing is employed. To prevent generation of minority carriers within the wells, on-chip filtering of power used for the devices in the wells and for biasing the wells is employed. Other techniques are used to reduce problems associated with minority carrier generation.
Claims14
In a metal-oxide-semiconductor (MOS) memory where a plurality of memory cells are fabricated in a well of a first conductivity type, said well being formed in a substrate of a second conductivity type, an improvement comprising:
- a separate distribution bus disposed on said substrate for providing power to said memory cells formed in said well and coupled to said well for biasing said well;
- and,
- a resistor formed on said substrate, in series with said bus for providing filtering of power distributed to said memory cells by said bus,
- whereby minority carrier generation in said well is reduced.
In a metal-oxide-semiconductor (MOS) dynamic random-access memory (RAM) where a plurality of memory cells are fabricated in an n-type well formed in a p-type substrate, an improvement comprising:
- a first and a second power distribution bus, said first power distribution bus being coupled to power, at least some decoders and buffers;
- said second power distribution bus being coupled to provide power to said memory cells and coupled to said well for biasing said well;
- a resistor formed on said substrate and coupled to said second bus for providing filtering of power distributed by said second bus;
- whereby minority carrier generation in said well is reduced.
Dependencies are inferred from the claim text.