A semiconductor memory device providing a plurality of data signals at a time, said semiconductor memory device comprising:
- a plurality of terminals, wherein the number of said terminals is equal to that of said data signals;
- a plurality of complementary common data line pairs which are disposed adjacent to each other, wherein the number of said common data lines is equal to that of said data signals;
- output means coupled between said terminals and common data line pairs;
- a plurality of unit memory arrays, each including a plurality of complementary data line pairs which are disposed adjacent to each other and a plurality of dynamic memory cells coupled to said data line pairs, wherein the number of said data line pairs in each of said unit memory arrays is equal to that of said common data line pairs, and wherein each of said dynamic memory cells includes a capacitor for storing data and a switching element coupled between said capacitor and the corresponding data line;
- column selecting means responsive to first address signals for designating a unit memory array from said unit memory arrays in accordane with first address signals;
- a plurality of unit column switching means, each coupled between said common data line pairs and the corrsponding unit memory array, wherein asid column switching means are controlled by said column selecting means so that each of the data line pairs in the unit memory array designated by said column selecting means is coupled to the corresponding common data line pair;
- a redundancy memory array including a plurality of complementary data line pairs which are disposed adjacent to each other and plurality of dynamic memory cells coupled to said data line pairs, wherein the number of said data line pairs is equal to that of said common data lines, and wherein each of said dynamic memory cells includes a capacitor for storing data and a switching element coupled between said capacitor and the corresponding data line;
- redundancy column switching means coupled between said common data line pairs and the redundancy memory array, said redundancy column switching means being responsive to a selection for coupling each of said data line pairs in said redundancy memory array to the corresponding common data line pair;
- and
- control means coupled to said column selecting means and said redundancy column switching means, said control means including means for generating said selection signal when said first address signals indicate a unit memory array including a defective memory cell and means for inhibiting the selection of a unit memory array including a defective memory cell from being done by said column selecting means when said first address signals indicate aunit memory array including a defective memory cell;
- whereby said output means receives data signals from said redundancy memory array instead of the unit memory array including the defective memory cell when said first address signals indicate the unit memory array including the defective memory cell.