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US 4,727,515 AGranted
High density programmable memory array
AssigneeGeneral Electric Company
InventorSheng T. Hsu
Life of this patent
Estimating the term…
Abstract
An array of electrically alterable floating gate devices arranged in rows and columns with each column of devices sharing a column conductor. Each row of devices is connected between two row conductors with adjacent rows sharing a common row conductor whereby in an array having N rows of devices there is a total of (N+1) row conductors. Input and output decoders connected to the row conductors enable the unique read-out of any selected element.
Claims9
The combination comprising:
- a plurality of electrically alterable floating gate devices arranged in N rows and M columns, each one of said devices having a control electrode and source and drain electrodes defining the ends of a conduction path, each one of said devices being of the type which assumes a first threshold voltage condition (V.sub.T1) when its gate is made positive with respect to its drain by more than a given voltage (V.sub.G) and which assumes a second threshold voltage condition (V.sub.T2) when its gate is made negative with respect to its drain by more than said given voltage;
- where N and M are integers greater than 2;
- M column conductors, one column conductor per column of devices, each column conductor being connected to the control electrodes of the devices of a column;
- N+1 row conductors, a pair [Ri and R(i+1)]of row conductors per row of devices, with each intermediate row (Ni) of devices, sharing one (Ri) of its pair of row conductors with a first [N(i-1)]adjacent row of devices positioned on one side of said intermediate row and sharing the other one [R(i+1)]of its pair of row conductors with a second [N(i+1)]adjacent row of devices positioned on the other side of said intermediate row;
- means connecting the source electrodes of the devices of each intermediate row.(Ni) and the drain electrodes of the devices of said first [N(i-1)]adjacent row to said one [Ri]of its pair of row conductors;
- and means connecting the drain electrodes of the devices of each intermediate row and the source electrodes of the devices of said second [N(i+1)]adjacent row to said other one [R(i+1)]of its pairs of row conductors;
- an input decoder having one output per row conductor, each output being connected to a different one of said row conductors for selectively supplying write and sense signals to said row conductors;
- an output decoder coupled to said row conductors for selectively sensing the signals present on a selected row conductor;
- and
- a gate decoder having one output per column conductor, each output being connected to a different one of said column conductors for selectively supplying sense and write signals to said column conductors.
7 more elements
The combination comprising:
- a plurality of electrically alterable floating gate devices arranged in rows and columns, each one of said devices having a control electrode, and source and drain electrodes defining the ends of a conduction path, each one of said devices being of the type which assumes a first threshold voltage condition (V.sub.T1) when its gate is made positive with respect to its drain by more than a given voltage (V.sub.G) and which assumes a second threshold voltage condition (V.sub.T2) when its gate is made negative with respect to its drain by more than said given voltage;
- a column conductor per column, each column conductor being connected to the control electrodes of the device of that column;
- a single row conductor per pair of adjacent rows, the drain electrodes of the devices of one row of a pair of adjacent rows being connected to said row conductor and the source electrodes of the other pair of the adjacent rows being connected to said row conductor;
- a first decoder having one output per row conductor coupled to said row conductors for selectively supplying signals to said row conductors;
- a second decoder coupled to each one of said row conductors having an output and including means for selectively coupling a selected one of said row conductors to said output;
- and
- a gate decoder having one output per column conductor for selectively supplying read and write signals to selected ones of said column conductors.
4 more elements
Dependencies are inferred from the claim text.