Programmable memory with memory cells programmed by addressing
AssigneeTexas Instruments Incorporated
InventorsRohit L. Bhuva, Allen Y. Chen
Life of this patent
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Abstract
A programmable memory includes a memory matrix (34) with a row decode circuit (36) and a column decode circuit (48) operable in the program mode to select one of the memory elements in the memory matrix (34). A current boost circuit (50) is operable to provide increased current to the selected cell such that selection of the cell opens the fuse associated therewith to change the logic state. The pins associated with the column and row addresses have multiple mode functions such that in the normal operating mode they can be assigned other tasks and in the programming mode are utilized primarily for addressing of the memory cells.
Claims16
A programmable memory, comprising:
- a matrix of programmable memory cells arranged in rows and columns, each cell for storing first and second logic states with each of said cells normally in the first logic state and programmable to the second logic state, said matrix in an operating mode having output lines coupled to respective groups of said columns;
- operating means for addressing select ones of said memory cells in the operating mode in accordance with an input operating address and for combining the logic states of said address cells in accordance with a predetermined operating logic function for output from said memory;
- program enable means for placing the memory in a programming mode to program said memory cells;
- means for addressing each cell in said matrix in the programming mode to program said memory cells;
- programming means for changing the logic state of an addressed one of said memory cells from the first logic state to the second logic state, said programming means activated in response to addressing one of said memory cells without raising the voltage on any of said output lines such that each of said memory cells is programmed in the programming mode by addressing thereof.
A programmable memory, comprising:
- a supply voltage input for receiving an external supply voltage;
- a plurality of input/output pins configurable in an operating mode to receive operating input addresses on select ones of said pins and provide outputs on select ones of said pins, and configurable in a programming mode to receive programming input addresses on select ones of said pins;
- a matrix of programmable memory cells arranged in rows and columns, each memory cell comprising a transistor having a base and an emitter-collector path with a fuse in series with said emitter-collector path and addressable with an address signal coupled to the base thereof, each of said memory cells connected on one side thereof to said supply voltage input for drawing current therefrom, a first logic state represented by said fuse being intact to allow current to flow therethrough and a second logic state being represented by said fuse being opened to prevent current flowing therethrough;
- a current sink associated with each of the columns in said matrix for sinking current through an associated one of said memory cells in the first logic state from said supply voltage when said associated memory cell in the first logic state is addressed;
- sense amp means associated with each of said columns for sensing current flow through an accessed one of said memory cells associated therewith to determine if current flows through the accessed one of said memory cells;
- operating means for addressing select ones of said memory cells in the operating mode in accordance with an operating input address and for combining the logic states output by said sense amp means for said addressed memory cells in accordance with a predetermined logic function for output on the output ones of said pins;
- program enable means for placing the memory in the programming mode and configuring said input/output pins in the programming mode;
- row access means for addressing each of the rows in said matrix in the programming mode in response to receiving an external programming row address from said pins;
- column access means for accessing each of said columns in the programming mode in response to receiving an external program column address;
- and
- program means for increasing the current through the accessed one of said memory cells in the programming mode to a level sufficient to open the associated one of said fuses without raising the voltage on any of said output pins.
A method for programming memory cells in a matrix of programmable memory cells arranged in rows and columns and accessed by input and output lines, each cells for storing first and second logic states with each of the cells normally in a first logic state and programmable to the second logic state, comprising:
- placing the matrix of memory cells in a programming mode;
- addressing in the programming mode each cell in the matrix in accordance with an external programming address;
- and
- changing the logic state of the addressed one of the memory cells in the first logic state to the second logic state in response to addressing of one of the memory cells such that each of the memory cells is programmed in the programming mode by addressing thereof without having to raise the voltage on any of the output lines of said programmable memory.
Dependencies are inferred from the claim text.