Circuit for adding and/or subtracting numbers in logarithmic representation
AssigneeMotorola, Inc.
InventorTim A. Williams
Life of this patent
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Abstract
In a digital signal processing system, a logarithmic arithmetic logic unit which selectively performs multiply/accumulate operations of operands in logarithmic number representation. Direct feed through of operands through an adder/subtractor circuit, even when an addition or subtraction is not effected, eliminates external bypass circuitry. A method for adding and subtracting operands in logarithmic number representation. An adder/subtractor circuit which efficiently effects addition and subtraction of operands in logarithmic number representation over a wide dynamic range.
Claims11
A circuit for adding or subtracting, in response to an arithmetic operation control signal, two numbers each of which has a logarithmic representation, comprising:
- first zero detection means having an input for receiving a first of the two numbers, a first output for providing the first number and a second output for providing a first zero detect control signal in response to detecting that the first number is a quantized zero logarithmic number;
- second zero detection means having an input for receiving a second of the two numbers, a first output for providing the second number and a second output for providing a second zero detect control signal in response to detecting that the second number is a quantized zero logarithmic number;
- first means having first and second inputs respectively coupled to the first output of the first and second zero detection means, said first means providing an absolute value of a difference of said two numbers an providing a first control signal indicating which one of said two numbers has a greater real value and a second control signal indicating if both numbers have equal real values;
- second means coupled to the first means for receiving the absolute value of the difference, said second means selectively providing a predetermined correction factor in response to the absolute value of the difference and providing a bypass control signal in response to the first or second zero detect control signal;
- and
- third means having a first input for selectively receiving the correction factor and a second input for selectively receiving the one of said two numbers having the greater real value in response to the first control signal, said third means selectively adding or subtracting the correction factor and said greatest real valued number to provide an output in logarithmic representation which is respectively either the sum or the difference of said two numbers, or directly outputting only the greatest real value number as the sum or difference in response to the bypass control signal, thereby avoiding a quantization error in the sum or difference output.
A circuit for adding or subtracting two logarithmic numbers, comprising:
- first means having first and second inputs, each input selectively receiving a predetermined one of said two numbers, said first means providing an absolute value of a difference of said two numbers and providing a first control signal indicating which one of said two numbers has a greater real valu and a second control signal indicating if both numbers have equal real values;
- second means coupled to the first means for receiving the absolute value of the difference, said second means selectively providing a predetermined correction factor in response to the absolute value of the difference and otherwise providing either a bypass control signal in response to one of the numbers having a quantized zero value or a zero quantization force isgnal in response to the second control signal;
- third means having a first input for selectively receiving the correction factor and a second input for selectively receiving the one of said two numbers having the greater real value in response to the first control signal, said third means selectively adding or subtracting the correction factor and said greatest real valued number to provide an output in logarithmic representation which is respectively either the sum or the difference of said two numbers, or directly outputting only the greatest real value number as the sum or difference in response to the bypass control signal;
- and
- fourth means coupled to the third means, for overriding the output of the third means in response to the zero quantization force signal and providing a predetermined quantized zero output value.
Dependencies are inferred from the claim text.