Multiplication circuit using a multiplier and a carry propagating adder
AssigneeFujitsu Limited
InventorHideo Miyanaga
Life of this patent
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Abstract
A multiplication circuit used for a high speed multiplier in a computer system is basically constituted by a multiplier and a carry propagating adder. The multiplier obtains a sum and carry per each bit by using carry save adder trees having a plurality of carry save adders, and generates a carry generation function and a carry propagation function based on the sum and carry by using a generation/propagation unit. The carry propagating adder obtains a final product based on the carry generation function and carry propagation function, and the carry generation function and carry propagation function generated by the generation/propagation unit are fed back to a final stage of the carry save adder.
Claims10
A multiplication circuit used for a high speed multiplication in a computer system, said multiplier circuit comprising:
- a multiplier including
- carrying save adder trees having a plurality of carry save adders for obtaining a sum and carry for a binary number, said carry save adder trees including at least a first stage carry save adder tree and a final stage carry save adder tree, and
- generation/propagation unit for generating a carry generation function and a carry propagation function based on said sum and carry, said carry generation function and said carry propagation function are fed back to said final stage carry save adder tree;
- and
- a carry propagating adder for obtaining a final product based on said carry generation function and said carry propagation function.
Dependencies are inferred from the claim text.